Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

Abstract: A readout device for a capacitive sense matrix includes a computer readable storage medium configured to store capacitance data. The capacitance data represents capacitance values of the capacitive sense matrix. The readout device also includes a readout circuit configured to receive a signal from the capacitive sense matrix, the readout circuit being configured based upon the capacitance data. Also described are a readout method and a method of compensating for variations in capacitance.

Abstract: Embodiments of the present disclosure are directed to a microfluidic delivery system that includes a microfluidic semiconductor die coupled to a flexible interconnect substrate to form an assembly. At least one embodiment is directed to a semiconductor die having an active surface that includes a layout that has electrically active bond pads along one side of the active surface of the die. A second side of the active surface of the die includes one or more mechanical pads.

Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Abstract: A probe card includes a number probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. The probes include at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. The probe card further includes at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.

Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.

Abstract: A voltage-current converter includes a first input stage and a second input stage with a first transistor and a second transistor driven by the first input stage and by the second input stage, respectively. First and second current generators are coupled to current lines of the first transistor and of the second transistor. At least one resistor couples the current lines of the first transistor and of the second transistor, where the ends of the aforesaid resistor are coupled to feedback terminals of the input stages so that an input voltage applied between voltage input terminals of the input stages is converted into a current on respective current output terminals of the converter. The converter includes switching circuits for coupling the first and second current generators alternately to the current line of the first transistor and to the current line of the second transistor.

Abstract: A method of compensated touch data values disclosed herein includes acquiring touch data values about a dead sensing zone of a touch screen, and determining a peak value of those touch data values. Then, a new peak value is calculated as a function of an average of the peak value and another value of the touch data value, and a sharpness value for the dead sensing zone is generated if a second highest value of the touch data values is less than the new peak value. Thereafter, compensated touch data values are generated for the dead sensing zone if the second highest value is greater than the new peak value.

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

Abstract: An optical module for use in a device includes an array of pixels configured to capture image data and a memory. The memory is configured to store identification information associated with said optical module. The identification information enables retrieval of information for controlling said optical module from a source outside said device.

Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

Abstract: A device of the Substitution-Box (S-Box) type, which is suitable for operating in a symmetric-key encryption apparatus, in particular an AES (Advanced Encryption Standard) encryption apparatus, and includes at least one module configured for carrying out a non-linear operation in a finite field (GF(28)) of an encryption method implemented by the above encryption apparatus, the module including at least one reprogrammable look-up table to, for example, implement countermeasures against side-channel attacks. When no countermeasures are employed, the tables may be set to fixed values, instead of being reprogrammable. The above module includes a plurality of composite look-up tables that implement the non-linear operation in a composite field of finite subfields (GF(24)2; GF((22)2)2) deriving from the finite field (GF(28)), each of the above composite look-up tables being smaller than a look-up table that is able to implement autonomously the non-linear operation in a finite field (GF(28)).

Abstract: A current limiting circuit includes a current sensing module that is configured to sense an output current of a power transistor and to generate a corresponding sensing current which is proportional to the output current. A first current limiting module coupled to the current sensing module is configured to generate a first limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a first current level. A second current limiting module coupled to the current sensing module is configured to generate a second limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a second current level. A converting module coupled to the first and second current limiting modules and the power transistor controls a gate voltage of the power transistor based at least on the first and second limiting currents.

Abstract: Disclosed herein is an electronic device including a first touch circuit to be coupled to a first touch sensing unit, the first touch sensing unit having first drive lines and first sense lines intersecting the first drive lines. A second touch circuit is to be coupled to a second touch sensing unit, the second touch sensing unit having second drive lines and second sense lines intersecting the second drive lines. A touch force circuit is to be coupled to a touch force sensing unit, the touch force sensing unit having third drive lines and third sense lines intersecting the third drive lines. The first touch circuit, second touch circuit, and touch force circuit are configured to drive the first, second, and third drive lines as a function of a synchronization signal, and acquire data from the first, second, and third sense lines as a function of the synchronization signal.

Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.

Abstract: Disclosed herein is a method including receiving a stream of packets into a buffer, each packet having a processed video data portion and a page count portion, the processed video data portion being a result of a modulo operation performed on a word of video data, and the page count portion being a data page number on which the word of video data is to be placed. Each packet is read from the buffer, and an output packet including the video data portion and a data tag portion is generated therefrom. The data tag portion is associated with, but does not directly represent, the data page number where the word of video data of the processed video data portion or of video data of a processed video data portion of a next packet, is to be placed. Each data tag portion contains fewer bits than each corresponding page count portion.

Abstract: A method of authenticating a slave device. The method includes initializing, by a host device, a charge retention circuit of the slave device, and receiving, by the host device, an indication of a discharge time of the charge retention circuit. The host device authenticates the slave device based on the received indication of the discharge time of the charge retention device.

Abstract: An embodiment is a powerline communications (PLC) apparatus including a communications interface that implements a first communication protocol including of a transceiver that communicates over an electrical power distribution wiring of a vehicle. The first communication protocol includes a powerline communications automotive network (PLCAN) delimiter type (DT) (PLCAN-DT), and a PLCAN variant length field in a frame control comprising payload length, a number of symbols used, a PHY block size, and a number of repetitions used, wherein broadcast addressing is used in the network to transmit messages.