Abstract: A microelectromechanical gyroscope includes: a substrate; a stator sensing structure fixed to the substrate; a first mass elastically constrained to the substrate and movable with respect to the substrate in a first direction; a second mass elastically constrained to the first mass and movable with respect to the first mass in a second direction; and a third mass elastically constrained to the second mass and to the substrate and capacitively coupled to the stator sensing structure, the third mass being movable with respect to the substrate in the second direction and with respect to the second mass in the first direction.
Type:
Grant
Filed:
December 9, 2015
Date of Patent:
January 16, 2018
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Daniele Prati, Carlo Valzasina, Luca Giuseppe Falorni, Matteo Fabio Brunetto
Abstract: An electronic device described herein includes a sensing unit having at least one sensor to acquire sensing data. An associated computing device extracts sensor specific features from the sensing data, and generates a motion activity vector, a voice activity vector, and a spatial environment vector as a function of the sensor specific features. The motion activity vector, voice activity vector, and spatial environment vector are processed to determine a base level context of the electronic device relative to its surroundings, with the base level context having aspects each based on the motion activity vector, voice activity vector, and spatial environment vector. Meta level context of the electronic device relative to its surroundings is determined as a function of the base level context, with the meta level context being at least one inference made from at least two aspects of the plurality of aspects of the base level context.
Type:
Grant
Filed:
March 18, 2016
Date of Patent:
January 16, 2018
Assignees:
STMicroelectronics, Inc., STMicroelectronics International N.V.
Inventors:
Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Kashif R. J. Meer, Indra Narayan Kar, Rajendar Bahl
Abstract: A control device for a converter of the switched-mode type provided with an inductor element and a switch element generates a driving signal for controlling switching of the switch element and determining alternately a phase of storage of energy in the inductor element as a function of an input quantity and a phase of transfer of the energy stored in the inductor element to an output element on which an output quantity is present; the control device generates the driving signal by means of a control based on the value of the output quantity in order to regulate the same output quantity. In particular, an estimation block determines an estimated value of the output quantity, and a driving block generates the driving signal as a function of said estimated value.
Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.
Type:
Grant
Filed:
November 24, 2015
Date of Patent:
January 16, 2018
Assignee:
STMICROELECTRONICS, INC.
Inventors:
John H. Zhang, Walter Kleemeier, Paul Ferreira, Ronald K. Sampson
Abstract: Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.
Type:
Grant
Filed:
June 26, 2017
Date of Patent:
January 16, 2018
Assignees:
STMicroelectronics (Grenoble 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
Abstract: A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.
Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.
Abstract: A system and method for multi-touch integrity sensing for a multi-touch capacitive touch screen is disclosed. The system and method determines a distinction between wanted touches, such as via a finger or stylus, and unwanted touches such as via foreign matter, errors, and the like.
Type:
Application
Filed:
July 5, 2016
Publication date:
January 11, 2018
Applicant:
STMicroelectronics Asia Pacific Pte Ltd
Abstract: A low dropout amplifier may include an error amplifier having first and second inputs coupled to a reference signal and a feedback signal, respectively. The error amplifier may be configured to generate first and second error signals at first and second outputs, respectively, with the first and second error signals based upon a difference between the reference signal and the feedback signal. A sink stage may be coupled to the first output and configured to generate a sink current based upon the first error signal. A source stage may be coupled to the second output and configured to generate a source current based upon the second error signal. An output node may be coupled to receive the sink and source currents.
Abstract: A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).
Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.
Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.
Abstract: A method of foreign matter rejection for multi-touch capacitive touch screens includes performing touch detection in both self-capacitance mode and mutual capacitance mode. By combining information from both modes, a distinction is identified between wanted touches, such as by a finger or stylus, and unwanted touches such as by foreign matter.
Type:
Application
Filed:
July 11, 2016
Publication date:
January 11, 2018
Applicant:
STMicroelectronics Asia Pacific Pte Ltd
Abstract: An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.
Type:
Grant
Filed:
October 12, 2016
Date of Patent:
January 9, 2018
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Davide Giuseppe Patti, Gianleonardo Grasso
Abstract: LED strings cascaded to one another are driven by an electronic circuit that includes regulation modules and a brightness-compensation module. The regulation modules carry out in sequence a current-regulation phase, in which they regulate the current that flows in the corresponding LED strings. The regulation module includes: a compensation regulator coupled to a compensation LED string and to a capacitor and a generator that generates an electrical quantity indicating the luminous flux emitted by the LED strings and by the compensation LED string. The compensation regulator regulates a current that flows in the compensation LED string as a function of the electrical quantity, discharging the capacitor through the compensation LED string.
Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
Abstract: A method of measuring the phase of a response signal relative to a periodic excitation signal, comprises the steps of producing for each cycle of the response signal two transitions synchronized to a clock and framing a reference point of the cycle; swapping the two transitions to confront them in turns to the cycles of the response signal; measuring the offsets of the confronted transitions relative to the respective reference points of the cycles; performing a delta-sigma modulation of the swapping rate of the two transitions based on the successive offsets; and producing a phase measurement based on the duty cycle of the swapping rate.
Abstract: A clock recovery circuit includes an oscillator to generate a clock signal. The oscillator varies a frequency of the clock signal as a function of a control signal. The clock recovery circuit has a phase tracking control loop to determine the phase error between the reference signal and the clock signal, and vary the control signal as a function of the phase error. The phase tracking control loop has a linear region for phase errors in the range between ?? and +?, thereby creating a cycle slippage event when the phase error exceed said range. The clock recovery circuit includes a cycle-slippage detector which determines whether the phase error reaches or approaches +? or ??. In case the phase error reaches or approaches +? or ??, the cycle-slippage detector acts on the control signal in an effort to avoid that said phase tracking control loop leaves said linear region.
Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.
Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.
Type:
Grant
Filed:
October 31, 2013
Date of Patent:
January 16, 2018
Assignee:
STMicroelectronics S.r.l.
Inventors:
Chantal Combi, Benedetto Vigna, Federico Giovanni Ziglioli, Lorenzo Baldo, Manuela Magugliani, Ernesto Lasalandra, Caterina Riva