Abstract: A control circuit includes a first control circuit generating a first drive control signal from a pre-drive signal (that is a frequency at which an opening angle of the first and second mirrors is equal) for the first mirror. A second control circuit generates a second drive control signal from the pre-drive signal for the second mirror. First and second drivers generate first and second drive signals for the first and second mirrors from the first and second drive control signals. The first and second drive control signals are generated so that the first and second drive signals each have a same frequency as the pre-drive signal but are different in amplitude from one another to cause the first and second mirrors to move at a same frequency, with a same and substantially constant given opening angle as one another, and in phase with one another.

Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.

Abstract: A pixel of an imager device includes a photosensitive area configured to integrate a light signal. A first capacitive storage node is configured to receive a signal representative of the number of charges generated by the photosensitive area. A second capacitive storage node is configured to receive a reference signal. A first transfer transistor is coupled between the first capacitive storage node and the photosensitive area. A second transfer transistor is coupled between the second capacitive storage node and a terminal which supplied the reference signal. The first and second two transfer transistors have a common conduction electrode and a common substrate, wherein the common substrate is coupled to the first capacitive storage node.

Abstract: A radio-frequency transceiver device includes a transmission circuit generating a transmission signal at a transmission pad connected to a transmission antenna by modulating a radio frequency signal as a function of a control signal. First and second reception circuits receive first and second signals at first and second reception pads connected to first and second reception antennas. The received first and second signals are demodulated via the radio frequency signal to generate first and second demodulated reception signals. A control circuit operates during a reception test phase to generate only the control signal in order to test, as a function of the first and second demodulated reception signals, whether the received first signal corresponds to the received second signal. A reception error signal indicating a reception error is generated when the test indicates that the received first and second reception signals do not correspond.

Abstract: An electronic device includes a carrier substrate having a front face and an electronic chip mounted on the front face. An encapsulation cover is mounted above the front face and bounds a chamber in which the chip is situated. A front opening is provided in front of an optical component of the chip. An optical element, designed to allow light to pass, is mounted on the cover in a position which covers the front opening of the cover. The optical element includes a central region designed to deviate light and a positioning pattern that is visible through the front opening. An additional mask is mounted on the encapsulation cover in a position which extends in front of the optical element. A local opening of the additional mask is situated in front of the optical component.

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.

Abstract: An elementary photonic interconnect switch is integrated into an optoelectronic chip and includes four simple photonic interconnect switches. Each simple photonic interconnect switch has two optical waveguides that cross and are linked by a ring resonator having one ring. A basic photonic interconnect switch, a complex photonic interconnect switch and/or a photonic interconnect network are integrated into an optoelectronic chip and including at least two elementary photonic interconnect switches.

Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.

Abstract: Transient overvoltage suppression is provided by discharging through a Metal Oxide Varistor (MOV) and Silicon Controlled Rectifier (SCR) which are connected in series between power supply lines. The SCR has a gate that receives a trigger signal generated by a triggering circuit coupled to the power supply lines. A trigger voltage of the triggering circuit is set by a Transil™ avalanche diode.

Abstract: A circuit has a first window comparator determining whether a signal at a first input has a voltage higher than a first threshold but lower than a second threshold, and a second window comparator determining whether a signal at a second input has a voltage higher than the first threshold but lower than the second threshold. A logic circuit generates pulses in response to either the first window comparator determining that the signal at the first differential input has a voltage higher than the first threshold but lower than the second threshold or the second window comparator determining that the signal at the second input has a voltage higher than the first threshold but lower than the second threshold. A filter circuit receives the pulses from the logic circuit and generates a flag indicating that the signal is invalid, based upon pulses received from the logic circuit.

Abstract: A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.

Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.

Abstract: An oscillator is coupled to a first side of a galvanic barrier for supplying thereto an electric supply signal. The oscillator is configured to be alternatively turned on and off as a function of a PWM drive signal applied thereto. A receiver circuit coupled to the galvanic barrier receives therefrom a PWM power control signal. A signal reconstruction circuit coupled between the receiver circuit block and the oscillator provides to the oscillator a PWM drive signal reconstructed from the PWM power control signal. The signal reconstruction circuit includes a PLL circuit coupled to the receiver circuit block and configured to lock to the PWM control signal from the receiver circuit block. A PLL loop within the PLL circuit is sensitive to the PWM drive signal applied to the oscillator. The PLL loop is configured to be opened as a result of the power supply oscillator being turned off.

Abstract: An electronic device includes a back cover, a display, a middle frame sandwiched between the display and the back cover, and a near field communications (NFC) antenna incorporated within the middle frame. An electronic board is positioned within the middle frame, and includes an NFC controller and a matching network coupled to the NFC controller. The matching network is configured to match impedances between the NFC antenna and the NFC controller.

Abstract: An oscillating structure includes first and second torsional elastic elements that define an axis of rotation and a moving element that is interposed between the first and second torsional elastic elements. The moving element, the first torsional elastic element and the second torsional elastic element lie in a first plane and are not in direct contact with one another. A coupling structure mechanically couples the moving element, the first torsional elastic element and the second torsional elastic element together. The moving element, the first torsional elastic element and the second torsional elastic element lie in a second plane different from the first plane. Oscillation of the moving element occurs as a result of a twisting of the first and second torsional elastic elements.

Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.

Abstract: A low drop-out (LDO) voltage regulator circuit includes a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node. A current regulation loop senses current flowing through the power transistor and modulates the control signal to cause the power transistor to output a constant current to the output node. A voltage regulation loop senses voltage at the output node and modulates the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated. The current regulation loop includes a bipolar transistor connected to the control terminal of the power transistor, where a base terminal of the bipolar transistor is driven by a signal dependent on a difference between the sensed current flowing through the power transistor and a reference.

Abstract: In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.