Abstract: A method includes selecting at least one first voltage that defines subsets of DC voltages from among an ordered set of DC voltages, comparing the first voltage with a DC reference voltage, selecting one of the subsets based on a result of the comparing, and comparing each voltage of the selected subset with the reference voltage.

Abstract: An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

Abstract: A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.

Abstract: A digital-to-analog converter (DAC) and a method for operating the DAC are disclosed. The DAC receives, over a first channel, a control signal that is transmitted in accordance with a binary protocol. The DAC also receives, over a second channel different than the first channel, data that is transmitted in accordance with a multilevel communication protocol that is different than the binary protocol. The DAC determines a plurality of first and second voltages based on the received data and identifies, based on the control signal, a time when data transmission or reception is switched between first and second antennas. In response to identifying, based on the control signal, the time when data transmission or reception is switched, the DAC outputs the determined plurality of first voltages to a first antenna tuning circuit or the determined plurality of second voltages to a second antenna tuning circuit.

Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium. In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.

Abstract: The process for starting a power supply circuit which includes a switched-mode power supply is performed using: a first phase during which, if an output voltage of the switched-mode power supply is lower than a first voltage, the switched-mode power supply operates in pulse width modulation mode to increase its output voltage up to said first voltage; and when the output voltage has reached the first voltage, a second phase during which the switched-mode power supply operates in a bypass mode.

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.

Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

Abstract: A sensing bridge includes first and second branches in parallel, the first branch including a first resistor in series with a first switch, the second branch including a second resistor in series with a second switch. Resistances of the resistors vary with a sensed physical variable. The branches switch between first and second phases, with the first switch closed and the second switch open during the first phase, and the first switch open and the second switch closed during the second phase. A reference block generates a control signal from the resistance of the variable resistors during the first and second phases. An oscillator generates an oscillating signal during the first and second phases from the variable sense current during the first and second phases. Processing circuitry determines a value of the sensed physical value from an algebraic combination of the oscillating signal during the first and second phases.

Abstract: A main carrier wafer includes a first integrated network of electronic connections between front and back faces. A first electronic chip is mounted to the front face of the main carrier wafer and connected to the network of electronic connections of the main carrier wafer. A secondary carrier wafer includes a platform that extends over the first chip and a base the protrudes backwards with respect to the platform to a back end face facing the main wafer. A second integrated network of electronic connections is provided within the secondary carrier wafer. A second electronic chip is mounted on top of the platform and connected to the second integrated network. The second integrated network is further connected to the main carrier wafer at the back end face.

Abstract: In accordance with embodiments, a first counter of a plurality of counters of an apparatus receives a plurality of pulse width signals in the time domain. The first counter generates a first increment signal in the time domain from the plurality of pulse width signals based on a first row of a Discrete Transform matrix. A synchronizer of the apparatus receives the first increment signal. The synchronizer generates a first synchronized increment signal in the time domain from the first increment signal. A first accumulator of a plurality of accumulators of the apparatus receives the first synchronized increment signal. The first accumulator accumulates the first synchronized increment signal over a period of time to generate a first frequency domain signal.

Abstract: An electronic chip is provided that includes a plurality of first transistors electrically coupled to one another in parallel. A plurality of first isolating trenches is included in the electronic chip, and the first transistors are separated from one another by the first isolating trenches. Each of the first isolation trenches has a depth and a maximum width, and the depth depends on, or is a function of, the maximum width.

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

Abstract: An electric transformer device (balun) is formed on a support plate having a first base face and an opposite second base face. The balun includes a first port (40) connectable to an electrical line for a differential signal and a second port connectable to an electrical line for a single-ended signal. A first printed conductive track is associated to the first base face of the support plate for connecting the first port to the second port. A printed conductive path is associated to the second base face of the support plate for connecting the first port to the second port. The printed conductive path is formed of a symmetric second and third printed conductive tracks.

Abstract: A self-supporting thin-film battery is manufacture by forming on the upper surface of a support substrate a vertical active stack having as a lower layer a metal layer having formed therein a first contact terminal of a first polarity of the battery and having formed therein as an upper layer a metal layer having a second contact terminal of a second polarity of the battery. A support film is then bonded to an upper surface of the upper layer. The lower layer is the separated from the substrate by projecting a laser beam through the substrate from a lower surface thereof to impinge on the lower layer.

Abstract: An integrated circuit includes a MOS transistor that is located in and on a semiconductor film of a silicon-on-insulator (SOI) substrate. The SOI substrate has, below a buried insulator layer, a first back gate region and two first auxiliary regions that are located, respectively, below source and drain contact regions of the MOS transistor. The conductivity type of the two first auxiliary regions is the opposite the conductivity type of the first back gate region. The conductivity type of the two first auxiliary regions is identical to the conductivity type of the source and drain contact regions of the MOS transistor.

Abstract: A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.

Abstract: Moisture that is possibly present in an integrated circuit is detected autonomously by the integrated circuit itself. An interconnect region of the integrated circuit includes a metal level with a first track and a second track which are separated by a dielectric material. A detection circuit applies a potential difference between the first and second tracks. A current circulating in one of the first and second tracks in response to the potential difference is measured and compared to a threshold. If the current exceeds the threshold, this is indicative of the presence of moisture which renders said dielectric material less insulating.