Abstract: A system, supplied by a power supply, is switched into standby mode by an electronic device that includes a charging input coupled to a charge voltage obtained from the voltage delivered by the power supply. A first input is coupled to the power supply and a power supply output is coupled to the system. A storage capacitive element is coupled to the charging input and configured to be charged by the charge voltage. A switching circuit, coupled between the first input and the power supply output, disconnects the power supply output from the first input when the voltage across the terminals of the storage capacitive element is higher than a threshold. A discharge circuit discharges the storage capacitive element so that the capacitor voltage becomes lower than the threshold. The switching circuit further re-connects the first input to the power supply output at the end of the discharge period.

Abstract: A Darlington switch in series with a biasing circuit is biased in an ON state by default to generate a supply voltage for a controller integrated circuit chip during start-up. On powering up, the supply voltage for the controller integrated circuit chip rises. When the supply voltage exceeds a minimum operating voltage threshold, the controller integrated circuit chip is enabled for operation and an auxiliary supply circuit begins generating the supply voltage for the controller integrated circuit chip. The Darlington switch is turned OFF when the supply voltage being generated by the auxiliary circuit is sufficiently higher than a threshold associated with the minimum operating voltage threshold. The circuit for controlling ON/OFF state of the Darlington switch has a substantially lower static power dissipation than the biasing circuit.

Abstract: A support substrate has first electric contacts in a front face. An electronic component is located above the front face of the support substrate and has second electric contacts facing the first electric contacts of the support substrate. An electric connection structure is interposed between corresponding first and second electric contacts of the support substrate and the electronic component, respectively. Each electric connection structure is formed by: a shim that is made of a first electrically conducting material, and a coating that is made of a second electrically conducting material (different from the first electrically conducting material). The coating surrounds the shim and is in contact with the corresponding first and second electric contacts of the support substrate and the electronic component.

Abstract: A piezoelectric transducer for energy-harvesting systems includes a substrate, a piezoelectric cantilever element, a first magnetic element, and a second magnetic element, mobile with respect to the first magnetic element. The first magnetic element is coupled to the piezoelectric cantilever element. The first magnetic element and the second magnetic element are set in such a way that, in response to relative movements between the first magnetic element and the second magnetic element through an interval of relative positions, the first magnetic element and the second magnetic element approach one another without coming into direct contact, and the interaction between the first magnetic element and the second magnetic element determines application of a force pulse on the piezoelectric cantilever element.

Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.

Abstract: A micro-electromechanical device includes a semiconductor substrate, in which a first microstructure and a second microstructure of reference are integrated. The first microstructure and the second microstructure are arranged in the substrate so as to undergo equal strains as a result of thermal expansions of the substrate. Furthermore, the first microstructure is provided with movable parts and fixed parts with respect to the substrate, while the second microstructure has a shape that is substantially symmetrical to the first microstructure but is fixed with respect to the substrate. By subtracting the changes in electrical characteristics of the second microstructure from those of the first, variations in electrical characteristics of the first microstructure caused by changes in thermal expansion or contraction can be compensated for.

Abstract: A method and apparatus for sensing a common mode feedback current are provided. The common mode feedback current may flow through a common mode resistive divider of a piezoresistive bridge. A first current mirror mirrors the common mode feedback current and provides a first mirrored common mode current. A current aggregation stage receives the first mirrored common mode current and determines a bridge current of the piezoresistive bridge based on the first mirrored common mode feedback current. A second current mirror may be used to mirror the first current mirror before determining the bridge current.

Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.

Abstract: The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.

Abstract: A metal oxide semiconductor (MOS) transistor has a source terminal, a drain terminal, a gate terminal and a body terminal. The source terminal is connected to receive a supply voltage and the body terminal is connected to receive a reverse body bias voltage. A photovoltaic circuit has a first terminal connected to the source terminal of the MOS transistor and a second terminal connected to the body terminal of the MOS transistor. The photovoltaic circuit converts received photons from the environment to generate the reverse body bias voltage.

Abstract: A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate.

Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.

Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.

Abstract: An electronic chip includes first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected. The first transistors are separated from one another by first isolating trenches. The chip also includes second transistors and second isolating trenches. The second transistors are separated from one another by the second isolating trenches. The first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.

Abstract: A distance from an apparatus to at least one object is determined by generating a first signal and generating light modulated by the first signal to be emitted from the apparatus. Light reflected by the at least one object is detected using a Time-of-flight detector array, wherein each array element of the Time-of-flight detector array generates an output signal from a series of photon counts over a number of consecutive non-overlapping time periods. The output signals are compared to the first signal to determine at least one signal phase difference. From this at least one signal phase difference a distance from the apparatus to the at least one object is determined.

Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.