Patents Assigned to STMicroelectronics (Crolles 2)
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Publication number: 20200350653Abstract: A hybrid coupler operating in a power divider mode includes two inputs, two outputs, a capacitive module coupled between the inputs and the outputs or on each input and each output. The capacitive module has an adjustable capacitive value making it possible to adjust the central frequency. A calibration method includes: delivering a first reference signal having a first reference frequency on the first input of the hybrid coupler, measuring the peak value of a first signal delivered to the first output of the coupler and measuring the peak value of a second signal delivered to the second output of the coupler. The two peak values are compared and an adjustment of the capacitive value of the capacitive module is made until an equality of the peak values is obtained to within a tolerance.Type: ApplicationFiled: November 21, 2017Publication date: November 5, 2020Applicant: STMicroelectronics SAInventors: Vincent KNOPIK, Jeremie FOREST, Eric KERHERVE
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Patent number: 10823826Abstract: A time of flight range detection device includes a laser configured to transmit an optical pulse into an image scene, a return single-photon avalanche diode (SPAD) array, a reference SPAD array, a range detection circuit coupled to the return SPAD array and the reference SPAD array, and a laser driver circuit. The range detection circuit in operation determines a distance to an object based on signals from the return SPAD array and the reference SPAD array. The laser driver circuit in operation varies an output power level of the laser in response to the determined distance to the object.Type: GrantFiled: May 25, 2017Date of Patent: November 3, 2020Assignee: STMicroelectronics, Inc.Inventors: Xiaoyong Yang, Rui Xiao, Arnaud Deleule
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Patent number: 10826268Abstract: A circuit includes a capacitance coupled between a high voltage node and ground, a laser diode having an anode coupled to the high voltage node and a cathode coupled to an output node, and a current source coupled between the output node and ground. The current source turns on based on assertion of a trigger signal and sinks current from the capacitance to ground to thereby cause the laser diode to lase, and turns off based on deassertion of the trigger signal. A clamping circuit is coupled between the output node and the high voltage node, and clamps voltage at the output node occurring when the current source switches off.Type: GrantFiled: June 27, 2019Date of Patent: November 3, 2020Assignees: STMicroelectronics S.r.l., Politecnico Di MilanoInventors: Marco Zamprogno, Alireza Tajfar
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Patent number: 10826384Abstract: A circuit includes an input node configured to receive an input reference signal. An output node is configured to provide a replica of the input reference signal with a respective scaling ratio to the input reference signal at the input node. A digital-to-analog converter has a reference input configured to receive the input reference signal from the input node, a digital input configured to receive a digital input signal having a digital signal value, and a digital-to-analog converter output configured to provide an output signal from the digital-to-analog converter resulting from conversion to analog of the digital input signal. The output node of the circuit is configured to sense the output signal from the digital-to-analog converter and to provide the replica of the input reference signal at the output node.Type: GrantFiled: July 8, 2019Date of Patent: November 3, 2020Assignee: STMicroelectronics S.r.l.Inventors: Giuseppe Calcagno, Alberto Cattani, Giuseppina Sapone
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Patent number: 10826880Abstract: A CAN device is provided with an encryption function and a decryption function. The encryption function allows messages to be encrypted and put onto a CAN bus. The decryption function allows the messages on the CAN bus to be decrypted. The encryption and decryption functions share keys which change over the course of time.Type: GrantFiled: March 29, 2018Date of Patent: November 3, 2020Assignees: STMicroelectronics (Grenoble 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETE, Energica Motor Company S.p.A.Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Giovanni Gherardi
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Patent number: 10824175Abstract: Devices, systems, and methods are provided for monitoring air flow through a server using differential pressure measurements. The device includes an external pressure sensor, an internal pressure sensor, and a controller that receives the pressures from the external and internal pressure sensors. The external pressure sensor detects air pressure of the ambient air around a server enclosure, the internal pressure sensor detects air pressure through a server enclosure, and the controller calculates a pressure differential between the pressure from the external pressure sensor and the internal pressure sensor. The controller can then generate a signal based on the pressure differential, the signal optionally controlling a cooling fan, generating an interrupt for the server circuitry, or performing some other action.Type: GrantFiled: July 24, 2018Date of Patent: November 3, 2020Assignee: STMicroelectronics, Inc.Inventor: Dominique Paul Barbier
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Publication number: 20200342930Abstract: A non-volatile memory integrated circuit has a memory plane organized into rows and into columns containing bit lines. The read amplifiers for each bit line are configured to generate an output signal on a read data channel. The read data channels respectively run through the memory plane along each bit line. Each read data channel is connected to all of the read amplifiers of the respective bit line.Type: ApplicationFiled: April 20, 2020Publication date: October 29, 2020Applicant: STMicroelectronics (Rousset) SASInventor: Francesco LA ROSA
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Publication number: 20200341917Abstract: A first communication interface is a contactless communication interface for an integrated circuit. A second communication interface is coupled to a processing unit external to the integrated circuit. The transfer of data between the first communication interface and the second communication interface is made in a transfer mode using a volatile memory circuit. The volatile memory circuit is accessible simultaneously or virtually simultaneously firstly to processing circuit coupled to said first communication interface and secondly to said processing unit via said second communication interface.Type: ApplicationFiled: April 20, 2020Publication date: October 29, 2020Applicant: STMicroelectronics (Rousset) SASInventor: Jose MANGIONE
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Publication number: 20200341763Abstract: A secure element includes a non-volatile memory. The non-volatile memory stores first instructions relating to pre-established security functions and at least one second instruction relating to at least one other personalized function. A processing unit executes at least one instruction from amongst the first instructions and the at least one second instruction obtained from the non-volatile memory.Type: ApplicationFiled: January 9, 2020Publication date: October 29, 2020Applicant: STMicroelectronics (Rousset) SASInventors: Laurent TABARIES, Jean-Luc BLANC, Yveline GUILLOUX
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Publication number: 20200343869Abstract: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.Type: ApplicationFiled: March 25, 2020Publication date: October 29, 2020Applicant: STMicroelectronics International N.V.Inventors: Nitin GUPTA, Prashutosh GUPTA
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Publication number: 20200342940Abstract: First and second memory arrays have common word lines driven by a row decoder in response to a row address. A first word line encoder associated with the first memory array encodes signals on the word lines to generate a first encoded value, and a second word line encoder associated with the second memory array encodes signals on the word lines to generate a second encoded value. Comparison circuitry compares the first encoded value to a first expected value (e.g., a first portion of the row address) and compares the second encoded value to a second expected value (e.g., a second portion of the row address). An error flag is asserted to indicate presence of a word line fault based upon a lack of match between the first encoded value and the first expected value and/or a lack of match between the second encoded value and the second expected value.Type: ApplicationFiled: April 13, 2020Publication date: October 29, 2020Applicant: STMicroelectronics International N.V.Inventors: Tanmoy ROY, Tanuj KUMAR, Shishir KUMAR
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Patent number: 10818669Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.Type: GrantFiled: August 24, 2018Date of Patent: October 27, 2020Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Abderrezak Marzaki, Arnaud Regnier, Stephan Niel, Quentin Hubert, Thomas Cabout
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Patent number: 10818721Abstract: An embodiment method of operating an imaging device including a sensor array including a plurality of pixels, includes: capturing a first low-spatial resolution frame using a subset of the plurality of pixels of the sensor array; generating, using a processor coupled to the sensor array, a first depth map using raw pixel values of the first low-spatial resolution frame; capturing a second low-spatial resolution frame using the subset of the plurality of pixels of the sensor array; generating, using the processor, a second depth map using raw pixel values of the second low-spatial resolution frame; and determining whether an object has moved in a field of view of the imaging device based on a comparison of the first depth map to the second depth map.Type: GrantFiled: August 22, 2018Date of Patent: October 27, 2020Assignee: STMicroelectronics (Research & Development) LimitedInventor: Neale Dutton
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Patent number: 10819245Abstract: A method of controlling synchronous rectification transistors in a switching converter includes sensing a drain-to-source voltage across each synchronous rectification transistor each switching half-cycle of the switching converter. An average of the sensed drain-to-source voltage is calculated for each synchronous rectification transistor over N prior switching half-cycles. A load current transient in the switching converter is sensed based on the sensed drain-to-source voltage of each synchronous rectification transistor and the calculated average of the sensed drain-to-source voltage for each synchronous rectification transistor over the N prior switching half-cycles.Type: GrantFiled: April 17, 2019Date of Patent: October 27, 2020Assignee: STMicroelectronics S.r.l.Inventors: Alberto Iorio, Emilio Volpi, Jeanpierre Vicquery
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Patent number: 10819236Abstract: A driver circuit generates a drive signal having a first and second voltage state for controlling a power transistor switch coupled to a power supply node. A control circuit operates to sense a supply voltage at the power supply node and compare the sensed supply voltage to one or more voltage thresholds. In response to the comparison, the control circuit adjusts a switching slope of the drive signal from the first voltage state to the second voltage state.Type: GrantFiled: October 7, 2019Date of Patent: October 27, 2020Assignee: STMicroelectronics (Rousset) SASInventor: Regis Roubadia
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Publication number: 20200335466Abstract: A bumping matrix includes many bumps, wherein each bump is rotationally asymmetric in a plane of the bumping matrix. The bumps are orientated in a centripetal arrangement. Bumps in a first portion of the bumping matrix have a first pitch in a first axis and bumps in a second portion of the bumping matrix have a second pitch in the first axis. The second pitch is different from the first pitch. Bumps have an oblong shape with a longer diameter and a shorter diameter. The centripetal arrangement orients the longer diameter of the bumps is a direction radially extending from a center of the bumping matrix.Type: ApplicationFiled: April 14, 2020Publication date: October 22, 2020Applicants: STMicroelectronics (Alps) SAS, STMicroelectronics (Grenoble 2) SASInventors: Laurent SCHWARTZ, David KAIRE, Jerome LOPEZ
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Publication number: 20200333399Abstract: A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.Type: ApplicationFiled: April 18, 2019Publication date: October 22, 2020Applicant: STMicroelectronics International N.V.Inventors: Venkata Narayanan SRINIVASAN, Shiv Kumar VATS, HIMANSHU
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Publication number: 20200336006Abstract: A first Radio-Frequency-to-Direct-Current (RF2DC) transducer receives a first signal from a sensing antenna and generates energy stored by an energy storage circuit. An energy transfer circuit is controllably switched between an energy storage state where energy is stored in the energy storage state and an energy transfer state where stored energy is transferred to a load. The voltage at the energy storage circuit is alternatively variable between an upper value and a lower value around a voltage setting point. A second RF2DC transducer, which is a down-scaled replica of the first RF2DC transducer, produces a second signal indicative of an open-circuit voltage of the first RF2DC transducer. The voltage setting point is set as a function of the second signal indicative of the open-circuit voltage of the first RF2DC transducer.Type: ApplicationFiled: April 15, 2020Publication date: October 22, 2020Applicant: STMicroelectronics S.r.l.Inventors: Roberto LA ROSA, Alessandro FINOCCHIARO
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Publication number: 20200336091Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Gwenael MAILLET, Jean-Louis LABYRE, Gilles BAS
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Publication number: 20200336138Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.Type: ApplicationFiled: April 15, 2020Publication date: October 22, 2020Applicants: STMicroelectronics S.r.l., STMicroelectronics (Alps) SASInventors: Giovanni Luca TORRISI, Domenico aka Massimo PORTO, Christophe ROUSSEL
