Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.

Abstract: Identical planar electronic components are stacked in an assembly. Each component has two contact metallizations positioned on edges of a same surface of the component. The components are stacked along a common axis. Each successive component is rotated about the common axis by a fixed angle. A value of the fixed angle is selected to position, side by side, the contact metallization of one component and the contact metallization of another next component adjacent to each other in the stack. Electrical connections are provided between two adjacent contact metallizations.

Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

Abstract: A touch screen controller includes input circuitry receiving touch data from the touch screen. Processing circuitry acquires touch data from the input circuitry in a self-capacitance sensing mode, locates a force island and locates a sense island. A length of the force island and a length of the sense island is calculated. If the length of the force island is greater than a threshold force length and if the length of the sense island is greater than a threshold sense length, then the product of the lengths is calculated, and if greater than a threshold size, designated a valid area. Touch data in the valid area is then acquired in mutual-capacitance sensing mode, and represents palm touch if a maximum strength value in the valid area is less than a maximum area threshold and if a minimum strength value in the valid area is greater than a minimum area threshold.

Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.

Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.

Abstract: A comparator circuit is implemented using a simple comparator core having two gain stages integrated in a single circuit block. The circuit operates with improved speed and resolution in comparison to a conventional continuous-time comparator. Offset trimming allows for the crossing time of the comparator to be adjusted close to an ideal crossing time.

Abstract: An integrated sensor device including a first die, housing a sensor element to detect a quantity external to the sensor device and transduce the external quantity into an electrical sensing signal; a second die mechanically coupled to the first die so that the first and second dies are stacked on one another along one and the same axis; and at least one heater of a resistive type integrated in the first die and/or in the second die, having a first conduction terminal and a second conduction terminal configured to couple respective first and second conduction terminals of a signal generator for causing an electric current to flow, in use, between the first and second conduction terminals of the heater and generate heat by the Joule effect. It is possible to carry out calibration in temperature of the sensor element.

Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.

Abstract: An example device has optical emitters for emitting incident radiation within a field of view and optical detectors for receiving reflected radiation. Based on the incident radiation and the reflected radiation, a histogram indicative of a number of photon events that are detected by the optical detectors over time bins is generated. The time bins is indicative of time differences between emission of the incident radiation and reception of the reflected radiation. The device further includes; a processor programmed to iteratively process the histogram by executing an expectation-maximization algorithm to detect a presence of objects located in the field of view of the device.

Abstract: An electronic device including a low dropout regulator having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node of the electronic device. A method for operating the device to switch into a power on mode includes: turning on the low dropout regulator, removing a DC bias from the second conduction terminal of the transistor, and turning on the transistor. A method for operating the device to switch into a power down mode includes: turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the low dropout regulator.

Abstract: A detection stage of an electronic detection device, for example a pH meter, includes an insulating region that receives an element to be analyzed. The insulating region is positioned on a sensing conductive region. A biasing stage includes an electrically conductive region which is capacitively coupled to the conductive region. The electrically conductive region is formed in an uppermost metallization level along with a further conductive region. That further conductive region is electrically connected to the sensing conductive region by a via passing through an insulating layer which insulates the electrically conductive region from the sensing conductive region.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

Abstract: An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer.

Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.

Abstract: A global shutter pixel includes a first transistor and a first switch series-connected between a first node of application of a potential and an internal node of the pixel. A control terminal of the first transistor is coupled to a floating diffusion node of the pixel. At least two assemblies are coupled to the internal node, where each assembly is formed of a capacitor series-connected with a second switch coupling the capacitor to the internal node. A second transistor has a control terminal connected to the internal node and a first conduction terminal coupled to an output node of the pixel. The pixel operation is controlled to store an initialization voltage from the floating diffusion on one of the capacitors and a pixel integration voltage from the floating diffusion on another of the capacitors.

Abstract: A MEMS device is formed in a die of semiconductor material having a cavity defined therein and having an anchorage portion. A tiltable structure is elastically suspended over the cavity and has a main extension in a horizontal plane. First and second supporting arms extend between the anchorage portion and opposite sides of the tiltable structure. First and second resonant piezoelectric actuation structures are intended to be biased to thereby cause rotation of the tiltable structure about a rotation axis. The first supporting arm is formed by first and second torsion springs, which are rigid to movements out of the horizontal plane and compliant to torsion about the rotation axis and are coupled together at a constraint region. The first and second resonant piezoelectric actuation structures extend between the anchorage portion and the constraint structure, on first and second sides of the first supporting arm.

Abstract: A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.

Abstract: A first electronic component, such as a sensor having opposed first and second surfaces and a first thickness, is arranged on a support member with the second surface facing towards the support member. A second electronic component, such as an integrated circuit mounted on a substrate and having a second thickness less than the first thickness, is arranged on the support member with a substrate surface opposed the second electronic component facing towards the support member. A package molding material is molded onto the support member to encapsulate the second electronic component while leaving exposed the first surface of the first electronic component. The support member is then removed to expose the second surface of the first electronic component and the substrate surface of the substrate.