Patents Assigned to STMicroelectronics (Crolles 2)
  • MATRIX IMAGING DEVICE COMPRISING AT LEAST ONE SET OF PHOTOSITES WITH MULTIPLE INTEGRATION TIMES
    Publication number: 20120305750
    Abstract: A method for controlling a pixel may include first and second photosites, each having a photodiode and a charge-transfer transistor, a read node, and an electronic read element, all of which are common to all the photosites. The method may include an accumulation of photogenerated charges in the photodiode of the first photosite during a first period, an accumulation of photogenerated charges in the photodiode of the second photosite during a second period shorter than the first period, a selection of the signal corresponding to the quantity of charges accumulated in the photodiode of a photosite having the highest unsaturated intensity or else a saturation signal, and a digitization of the selected signal.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic Barbier, Frederic Lalanne
  • PROCESS FOR FABRICATING A BACKSIDE-ILLUMINATED IMAGING DEVICE AND CORRESPONDING DEVICE
    Publication number: 20120306035
    Abstract: An integrated imaging device includes a silicon layer provided over a dielectric multilayer. The dielectric multilayer includes a top silicon-dioxide layer, an intermediate silicon-nitride layer and a bottom silicon-dioxide layer. Imaging circuitry is formed at a frontside of the silicon layer. An isolating structure surrounds the imaging circuitry and extends from the frontside through the silicon layer and top silicon-dioxide layer into and terminating within the intermediate silicon-nitride layer. A filter for the imaging circuitry is mounted to a backside of the bottom silicon-dioxide layer. The isolating structure is formed by a trench filled with a dielectric material.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 6, 2012
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Roy, Francois Leverd, Jens Prima
  • Method for producing a membrane comprising micropassages made from porous material by chemical mechanical polishing
    Patent number: 8323733
    Abstract: A surface of a support comprising through micropassages is brought into contact with an aqueous solution comprising a plurality of particles in suspension and a pad. A pressure perpendicular to the plane of the support, between the pad and the surface of the support, and a relative movement of the pad and of the surface in a direction parallel to the plane of the support are applied. At least one particle is thus introduced in each microgap to form a porous material therein.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: December 4, 2012
    Assignees: Commisariat a l'Energie Atomique, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Christophe Coiffic, Maurice Rivoire
  • SRAM memory cell with four transistors provided with a counter-electrode
    Patent number: 8314453
    Abstract: The memory cell is of SRAM type with four transistors provided with a counter-electrode. It comprises a first area made from semiconductor material with a first transfer transistor and a first driver transistor connected in series, their common terminal defining a first electric node. A second transfer transistor and a second driver transistor are connected in series on a second area made from semiconductor material and their common terminal defines a second electric node. The support substrate comprises first and second counter-electrodes. The first and second counter-electrodes are located respectively facing the first and second semiconductor material areas. The first transfer transistor and second driver transistor are on a first side of a plane passing through the first and second electric nodes whereas the first driver transistor and second transfer transistor are on the other side of the plane.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: November 20, 2012
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Thomas, Claire Fenouillet-Béranger, Philippe Coronel, Stéphane Denorme
  • EFFECTING SELECTIVITY OF SILICON OR SILICON-GERMANIUM DEPOSITION ON A SILICON OR SILICON-GERMANIUM SUBSTRATE BY DOPING
    Publication number: 20120282747
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.
    Type: Application
    Filed: October 24, 2011
    Publication date: November 8, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondot, Markus Gerhard Andreas Muller, Thomas Kormann
  • MICROELECTRONIC CHIP, COMPONENT CONTAINING SUCH A CHIP AND MANUFACTURING METHOD
    Publication number: 20120273952
    Abstract: Microelectronic chip including a semiconductor substrate; at least one area of its surface which is suitable to be electrically connected to a metal frame designed to accommodate the chip; at least one interconnect area formed by a copper-based conductive layer and comprising a connecting device, the interconnect area being connected to the area by a conductor, wherein the area is formed by a layer forming a copper diffusion barrier inserted between interconnect area and the substrate.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Laurent Gay, Francois Guyader, Frederic Diette
  • Process for producing a contact pad on a region of an integrated circuit, in particular on the electrodes of a transistor
    Patent number: 8299541
    Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: October 30, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Damien Lenoble, Philippe Coronel, Robin Cerutti
  • Method for forming electric vias
    Patent number: 8298942
    Abstract: A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: October 30, 2012
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Richard Fournel, Yves Dodo
  • Increasing the capacitance of a capacitive device by micromasking
    Patent number: 8295028
    Abstract: Capacitive coupling devices and methods of fabricating a capacitive coupling device are disclosed. The coupling device could include a stack of layers forming electrodes and at least one insulator. The insulator could include a region of doped silicon. The silicon could be doped with a species selected from Ce, Cr, Co, Cu, Dy, Er, Eu, Ho, Ir, Li, Lu, Mn, Pr, Rb, Sm, Sr, Tb, Tm, Yb, Y, Ac, Am, Ba, Be, Cd, Gd, Fe, La, Pb, Ni, Ra, Sc, Th, Hf, Tl, Sn, Np, Rh, U, Zn, Ag, and Yb in relief and forming roughnesses relative to the neighboring regions of the same level in the stack. The electrodes and the insulator form conformal layers above the doped silicon region.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: October 23, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Benoit Froment
  • Method and device for driving the frequency of a clock signal of an integrated circuit
    Patent number: 8294508
    Abstract: An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: October 23, 2012
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Robin Wilson, Sylvain Engels, Eric Balossier
  • BACK-SIDE ILLUMINATED IMAGE SENSOR PROVIDED WITH A TRANSPARENT ELECTRODE
    Publication number: 20120261783
    Abstract: A back-side illuminated image sensor formed from a thinned semiconductor substrate, wherein: a transparent conductive electrode, insulated from the substrate by an insulating layer, extends over the entire rear surface of the substrate; and conductive regions, insulated from the substrate by an insulating coating, extend perpendicularly from the front surface of the substrate to the electrode.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 18, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Jens PRIMA, François ROY, Michel MARTY
  • METHOD FOR FORMING A BACK-SIDE ILLUMINATED IMAGE SENSOR
    Publication number: 20120261732
    Abstract: A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) thinning the substrate from its rear surface; b) depositing, on the rear surface of the thinned substrate, an amorphous silicon layer of same conductivity type as the substrate but of higher doping level; and c) annealing at a temperature enabling to recrystallized the amorphous silicon to stabilize it.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 18, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Michel Marty, François Roy, Jens Prima
  • BACK-SIDE ILLUMINATED IMAGE SENSOR WITH A JUNCTION INSULATION
    Publication number: 20120261670
    Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 18, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Michel Marty, François Roy, Jens Prima
  • METHOD FOR FORMING A BACK-SIDE ILLUMINATED IMAGE SENSOR
    Publication number: 20120261784
    Abstract: A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) forming, from the front surface of the substrate, areas of same conductivity type as the substrate but of higher doping level, extending deep under the front surface, these areas being bordered with insulating regions orthogonal to the front surface; b) thinning the substrate from the rear surface to the vicinity of these areas and all the way to the insulating regions; c) partially hollowing out the insulating regions on the rear to surface side; and d) performing a laser surface anneal of the rear surface of the substrate.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 18, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: François Roy, Michel Marty
  • METHOD FOR CONTROLLING THE ELECTRICAL CONDUCTION BETWEEN TWO METALLIC PORTIONS AND ASSOCIATED DEVICE
    Publication number: 20120248568
    Abstract: A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Serge Blonkowski
  • PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS
    Publication number: 20120252174
    Abstract: A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Didier Dutartre, Nicolas Loubet, Yves Campidelli, Denis Pellissier-Tanon
  • Scalloped tubular electric via
    Patent number: 8274139
    Abstract: A via connecting the front surface of a substrate to its rear surface and having, in cross-section in a plane parallel to the surfaces, the shape of a scalloped ring.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: September 25, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Hamed Chaabouni, Lionel Cadix
  • THERMOELECTRIC GENERATOR
    Publication number: 20120228992
    Abstract: A thermoelectric generator including a sheet of a deformable material containing closed cavities, each of which contains a drop of a vaporizable liquid, and a mechanism for transforming into electricity the power resulting from the deformation of the sheet linked to the evaporation/condensation of the liquid.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 13, 2012
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Thomas Skotnicki
  • Bus with error correction circuitry
    Patent number: 8266494
    Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: September 11, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Richard Ferrant, Cédric Maufront
  • Single-crystal semiconductor layer with heteroatomic macro-network
    Patent number: 8263965
    Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: September 11, 2012
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Yves Campidelli, Oliver Kermarrec, Daniel Bensahel