Abstract: An apparatus is adapted to test a power supply device of the USB-PD type which includes at least one USB Type-C connector. The USB Type-C connector is intended to be connected to the power supply device to be tested. The device is separate from the apparatus.

Abstract: A variable duty cycle switching signal at a switching frequency is applied to a switching current regulation circuit arrangement energizing a current storage circuit assembly. Switching of the variable duty cycle switching signal is controlled by an upper and a lower threshold current level. The upper and lower threshold current levels vary with time following an average current value time variation. Additionally, frequency jitter is introduced in the variable duty cycle switching signal by: defining at least a frequency modulation window around a limit frequency identifying a limit value for an acceptable EMI; and applying an amplitude modulation of the upper and/or lower threshold current levels varying with time, wherein the amplitude modulation is applied in a time interval between times when the switching frequency enters and exit the frequency window.

Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

Abstract: A method includes performing, by a terminal with an access card, a first relay attack check for the access card in accordance with a local value associated with the terminal and a local value associated with the access card; determining, by the terminal, that the access card has passed the first relay attack check, and based thereon, performing, by the terminal with the access card, an authentication check of the access card in accordance with the local value associated with the terminal, the local value associated with the access card, and a local challenge value associated with the terminal; and determining, by the terminal, that the access card has passed the first relay attack check and the authentication check, and based thereon, validating, by the terminal, the access card.

Abstract: A device for discharging a capacitor includes a resistive component having a resistance value selectable from among at least three resistance values. The device is configured to be connected in parallel with the capacitor. A circuit operates to select the resistance value of the resistive component.

Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.

Abstract: A method is presented for manufacturing an insulated conductive via. The via crosses a first stack of layers to reach a first layer. A first cavity is formed partially extending into the first stack of layers. A second stack of layers is formed over the first stack of layers and in the first cavity. The second stack of layers includes an etch stop layer and an insulating layer. A second cavity is then formed extending completely through first and second stacks of layers to reach the first layer. An insulating liner then covers the walls and bottom of the second cavity. The insulating liner is then anisotropically etched, and the second cavity is filled by a conductive material forming the core of the via.

Abstract: An avalanche photodiode includes a stack of layers. The stack of layers includes an avalanche diode (of PN or PIN type) and a layer having quantum dots located therein. The stack of layers further includes: a charge extraction layer over the layer which includes quantum dots; a transparent conducting layer over the charge extraction layer; and an insulating layer over the transparent conducting layer. The quantum dots includes ligands formed by molecules of dopants.

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

Abstract: An embodiment of the present description concerns a method wherein a duration of a periodic step of activation of a near-field communication circuit of a first device is calibrated according to a time interval between an activation of the circuit and a reception, by the first device, of a message transmitted by a second device.

Abstract: A system for detection of a touch gesture of a user on a detection surface includes a processing unit, an electrostatic-charge-variation sensor, which generates a charge-variation signal; and an accelerometer, which generates an acceleration signal. The processing unit is configured to: detect, in the charge-variation signal, a first feature identifying the touch; detect, in the acceleration signal, a second feature identifying the touch; detect a temporal correspondence between the first and second features identifying the touch gesture; and validate the touch gesture only in the case where both the first and second features have been detected and the temporal correspondence satisfies a pre-set relation.

Abstract: A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.

Abstract: An embodiment DC switching converter comprises first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.

Abstract: A heat dissipation device includes a substrate with a network of thermally-conductive vias and thermally-conductive layers. The substrate has a first surface and a second surface opposite to the first surface. A heat dissipation interface layer including a stack of a first layer made of a first thermally-conductive material and a second layer made of a second thermally-conductive material. The first material is different from the second material. A surface of the first layer is coplanar with the first surface of the substrate. At least one of the thermally-conductive vias of said network supports and is in contact with the first layer. At least one opening thoroughly crosses the stack of the first and second layers. Material of the substrate fills the opening in the first layer.

Abstract: A “double-deck” semiconductor device includes a first semiconductor chip mounted to a first surface of a leadframe, with a first wire bonding pattern and a first mass of encapsulating material molded onto the first surface of the leadframe when the leadframe is in a first spatial orientation. The leadframe with the first semiconductor chip and the first wire bonding pattern encapsulated and thus protected by the first mass of encapsulating material is then turned over to a second spatial orientation. A second semiconductor chip is attached to the second surface of the leadframe, with a second wire bonding pattern and a second mass of encapsulating material, different from the first mass of encapsulating material molded onto the second surface of the leadframe.

Abstract: A tray carrier includes a base plate having a first and second pairs of opposed sides as well as opposed first and second surfaces. Channel-shaped corner members provide containment formations for trays stacked at the first surface of the base plate. Tray carrier gripping cavities provided in the first pair of opposed sides can be engaged by gripping formations of an automated gripper to facilitate gripping the tray carrier. Raised portions at the first surface of the base plate provide a tray-gripping space engaged by gripping formations of the automated gripper to facilitate gripping trays stacked at the first surface of the base plate. Handle members at the second sides of the base plate facilitate manual handling of the tray carrier, and a pair of opposed recesses in the first sides of the base plate provide a narrowed intermediate portion of the base plate for manual handling of trays.

Abstract: An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.

Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.