Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

Abstract: Methods of operating an induction geyser include drawing current through a resonant tank via a transistor, generating a changing magnetic field around the resonant tank. Owing to the strategic placement of the resonant tank in proximity to a fluid tank, the changing magnetic field envelopes the fluid tank. In a first method, the voltage across the transistor's conduction terminals is monitored, and when this voltage surpasses a predefined threshold, indicating an overvoltage condition, a corrective action is initiated in which a gate driver pulls up a gate drive signal that drives the transistor. In a second method, the current flowing between the transistor's conduction terminals is monitored, and upon detecting an overcurrent condition where the current exceeds a set threshold the gate driver is activated to pull down the gate drive signal. Both methods aim to keep operation of the geyser within desired parameters.

Abstract: The present disclosure is directed to a device and method for lid angle detection that is accurate even if the device is activated in an upright position. While the device is in a sleep state, first and second sensor units measure acceleration and angular velocity, and calculate orientations of respective lid components based on the acceleration and angular velocity measurements. Upon the device exiting the sleep state, a processor estimates the lid angle using the calculated orientations, sets the estimated lid angle as an initial lid angle, and updates the initial lid angle using, for example, two accelerometers; two accelerometers and two gyroscopes; two accelerometers and two magnetometers; or two accelerometers, two gyroscopes, and two magnetometers.

Abstract: The present disclosure is directed to a device and method for lid angle detection that is accurate even if the device is activated in an upright position. While the device is in a sleep state, first and second sensor units measure acceleration and angular velocity, and calculate orientations of respective lid components based on the acceleration and angular velocity measurements. Upon the device exiting the sleep state, a processor estimates the lid angle using the calculated orientations, sets the estimated lid angle as an initial lid angle, and updates the initial lid angle using, for example, two accelerometers; two accelerometers and two gyroscopes; two accelerometers and two magnetometers; or two accelerometers, two gyroscopes, and two magnetometers.

Abstract: A LED driver chip includes driver circuits, each being coupled to a different pin and including a fault-detection circuit. Each fault-detection circuit includes a force circuit forcing current to a force node, and a sense circuit including a current sensor coupled to the force node, and a comparator comparing a voltage at the force node to a reference voltage to generate a comparison output. Control circuitry, in a pin-to-pin short detection mode, activates the force circuit of a first of the driver circuits and activates the sense circuit of a second of the driver circuits, in a pin-to-ground short detection mode, activates the force and the sense circuit of the same driver circuits. The comparison output of the comparator of the activated sense circuit, if is higher or if lower of the reference voltage, indicates if short between pin or to ground, respectively, is present.

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

Abstract: A method for mutual authentication that includes establishing a first inductive coupling between a wireless-power receiver and a wireless-power transmitter to transfer power from the wireless-power transmitter to the wireless-power receiver by a power signal and using the power signal to transmit a first response to a physically unclonable function to the wireless-power transmitter. The method further including generating a second response to the physically unclonable function and communicating information derived from the second response to initiate a mutual authentication process between the wireless-power receiver and the wireless-power transmitter during a subsequent inductive coupling.

Abstract: Cryptographic circuitry, in operation, generates N first pairs of elliptic curve cryptography (ECC) keys r(i), R(i), with i varying from 1 to N, using K second pairs of ECC keys p(k), P(k), with k varying from 1 to K, wherein K is smaller than N. Each pair r(i), R(i) of the first pairs of keys is a linear combination of pairs of the second pairs of ECC keys according to: ? i ? [ 1 ; N ] ? { r ? ( l ) = ? j = 1 K A ? ( i , j ) * p ? ( j ) R ? ( i ) = ? j = 1 K A ? ( i , j ) * P ? ( j ) , wherein A(i,j) designates a general term of a matrix A of size N*K, and all the sub-matrices of size K*K are invertible. The cryptographic circuitry, in operation, executes cryptographic operations using one or more pairs of the first pairs of ECC keys.

Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.

Abstract: The present disclosure is directed to an optical sensor package with a first assembly and a second assembly with an encapsulant extending between and coupling the first assembly and the second assembly. The first assembly includes a first substrate, a first die on the first substrate, a transparent material on the first die, and an infrared filter on the transparent material. The second assembly includes a second substrate, a second die on the second substrate, a transparent material on the second die, and an infrared filter on the transparent material. Apertures are formed through the encapsulant aligned with the first die and the second die. The first die is configured to transmit light through one aperture, wherein the light reflects off an object to be detected and is received at the second die through another one of the apertures.

Abstract: An embodiment electronic circuit power supply device is configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node; regulate a potential of the node to a constant value by acting on the third current; flow a fourth constant current through a third conductor connected to the node; and consume a fifth current that is an image of the third current.

Abstract: An embodiment method of measuring ambient light comprises generating, by an ambient light sensor associated with a screen which alternates between first phases in which light is emitted and second phases in which no light is emitted by the screen, a first signal representative of an intensity of light received by the ambient light sensor during the first and second phases; comparing the first signal with a threshold intensity value; and controlling a timing of an ambient light measurement by the light sensor based on the comparison.

Abstract: A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

Abstract: The present description concerns an electronic device comprising a stack of a Schottky diode and of a bipolar diode, connected in parallel by a first electrode located in a first cavity and a second electrode located in a second cavity.

Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.

Abstract: A system and method for wireless charging a wireless earbud. The wireless earbud having a body that includes a passive magnetic shield and a coil. The coil is wound around a portion of the body comprising the passive magnetic shielding. The wireless earbud receiving wireless energy in response to the placement of the body within an electromagnetic field, which results in the charging of a battery of the wireless earbud.

Abstract: Various embodiments provide an apparatus and method for fabricating a wafer, such as a SiC wafer. The apparatus includes a support having a plurality of arms for supporting a substrate. The arms allows for physical contact between the support and the substrate to be minimized. As a result, when the substrate is melted, surface tension between the arms and molten material is reduced, and the molten material will be less likely to cling to the support.