Abstract: An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry.

Abstract: An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.

Abstract: An amplifier for amplifying an input signal in a frequency band, has a quadrature signal divider for dividing the input signal into first and second components. The first component is amplified in a first transistor amplifier having a first frequency response to produce a first amplified component. The second component is amplified in second transistor amplifier having a second frequency response, different to the first frequency response, to produce a second amplified component. The first and second amplified components are combined in a quadrature signal combiner to produce an amplified input signal. The frequency response of the amplifier is related to the sum of the first frequency response and second frequency response.

Abstract: An acceleration sensor includes a semiconductor substrate, a first layer formed on the substrate, a first aperture within the first layer, and a beam coupled at a first end to the substrate and suspended above the first layer for a portion of the length thereof. The beam includes a first boss coupled to a lower surface thereof and suspended within the first aperture, and a second boss coupled to an upper surface of the second end of the beam. A second layer is positioned on the first layer over the beam and includes a second aperture within which the second boss is suspended by the beam. Contact surfaces are positioned within the apertures such that acceleration of the substrate exceeding a selected threshold in either direction along a selected axis will cause the beam to flex counter to the direction of acceleration and make contact through one of the bosses with one of the contact surfaces.

Abstract: A programmable system device includes an embedded FLASH memory module and an embedded programmable logic device (PLD) module. A sole embedded power supply voltage generator generates a plurality of voltages for use by the FLASH memory module and the PLD module during programming, reading and erasing operations. A switching network receives at least some of the generated voltages and selectively chooses among and between the received generated voltages for application to the FLASH memory module and the PLD module depending on whether that particular module is engaged in programming, reading or erasing operations. A load adjustment circuit controls operation of the sole power supply voltage generator based on whether the generated voltages are being used by the FLASH memory module or the PLD module to account for differences in loading between the FLASH memory module and the PLD module during programming, reading and erasing operations.

Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.

Abstract: A system and method for transmitting and receiving secure e-mails is disclosed. A smart card device stores both private and public keys for an encryption algorithm. The smart card device is preferably a USB smart card device and interfaces a host having a client e-mail program. E-mails are transferred to and/or from the client e-mail program and e-mail server via the smart card while decrypting and encrypting any transmitted and/or received e-mails within the smart card device. The smart card device stores an IP address for an e-mail server. A Simple Mail Transfer Protocol outgoing parameter is set from the client e-mail program to an IP address for the smart card device.

Abstract: A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includes a plurality of transmitter cells consisting of a driver cell and digital to analog converter connected to driver cell. A hybrid circuit connects between the transmitter outputs and receiver inputs for separating a receiver signal from the transmitter signal responsive to a tuning signal.

Abstract: A plasma chamber is provided having an upper insulating member as a lid of the plasma chamber. The lid of the plasma chamber, usually in the form of a bell jar, has an inside surface which will be exposed to the interior of the plasma chamber. A nucleation layer is affixed to the inside surface of the insulating member. The nucleation layer is selected to be a material which will enhance the growth on itself of the particular material being etched within the process chamber. For example, if the pre-clean chamber is being used to etch oxides, the nucleation layer is selected to be of a type which will create a large number of nucleation sites for the growth of an oxide layer on the interior wall of the bell jar. Each nucleation site becomes the starting point for the adherence of the etched oxide atoms onto the wall of the bell jar. Wafers pre-cleaned in such a chamber have a lower defect density. Further, longer times are permitted between cleaning and replacing components in the pre-clean chamber.

Abstract: A memory cell includes first and second p-channel transistors and first and second n-channel transistors in a cross-coupled latch configuration. Power control circuitry associated with the memory cell is coupled to selectively perform voltage transitions on the source terminals of one or more of the n-channel and/or p-channel transistors in the memory cell during a data corruption mode of operation to destroy data stored in the latch and set the memory cell to a known state. In one implementation, the power control circuitry is coupled to the source terminal of one of the n-channel transistors to transition that terminal from a low voltage reference level (present during a normal mode of operation) to a high voltage reference level and back to the low voltage reference level. In another implementation, the power control circuitry is coupled to the source terminal of one of the n-channel transistors and the source terminal of at least one of the p-channel transistors.

Abstract: A method for characterizing a read channel of a disk drive by storing a pseudorandom number (PN) sequence at a first location on a recording surface of the disk drive, and storing the PN sequence at a second location on the recording surface. The PN sequence at the first location is read to generate a first playback signal, and a first dibit response is determined from the first playback signal. The PN sequence at the second location is read to generate a second playback signal, and a second dibit response is determined from the first playback signal. The first and second dibit responses are arithmetically combined to generate a combined dibit response in which at least some non-linear echoes are isolated.

Abstract: To improve the performance of DSL modems, a DSL duplexing ratio for a new communication is selected according to the communications needs of an application. A required upstream and downstream bit rate for application communications is determined. From the ratio of these bit rates, a desired duplexing ratio is calculated. The operation of the modem is then adapted to choose a duplexing ratio that approximates the desired duplexing ratio for the application. To optimize modem operation, the size and position of the upstream and downstream bandwidths used for transmission are intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by the chosen duplexing ratio. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated.

Abstract: A programmable priority encoder is disclosed for use with the device such as a Content Addressable Memory (CAM) device having a plurality of array objects to be encoded in binary and arranged in row and columns. Match lines are adapted to be connected to a plurality of arrayed objects associated with respective rows. A plurality of encoder cells, each having a memory element and forming an encoder block are arranged in rows. Precharged bus lines are operative with the encoder cells and match lines. The precharged bus lines are discharged indicating a match and priority is assigned to rows based on logic values stored within the memory elements of the encoder cell.

Abstract: A method and apparatus for processing multimedia instruction enhanced data by the use of an abstract routine generator and a translator. The abstract routine generator takes the multimedia instruction enhanced data and generates abstract routines to compile the multimedia instruction enhanced data. The output of the abstract generator is an abstract representation of the multimedia instruction enhanced data. The translator then takes the abstract representation and produces code for processing.

Abstract: There is disclosed a digital video recorder that uses a circular file management system to efficiently manage time-shifted viewing a live video broadcast television program. There is provided for use in the digital video recorder, an apparatus for performing time-shifted viewing of an incoming television program being received by the digital video recorder. The apparatus comprises a controller capable of creating a data file having a defined maximum size on a storage disk of the digital video recorder and capable of causing video data associated with the incoming television program to be stored sequentially in the data file from a first location to an Nth location. The controller, in response to a determination that the video data has been stored in the Nth location, causes a next received video data to be stored in the first location.

Abstract: A hardware command queue for mass storage systems having a memory device. A plurality of entries are defined in the memory device, at least some of which are active entries. At least some of the active entries correspond to pending access commands and at least one entry is a head entry corresponding to an in-flight access command.

Abstract: A method includes receiving an activation signal at a semiconductor device and generating an output power signal at the semiconductor device in response to receiving the activation signal. The output power signal has a duty cycle. The method also includes providing the output power signal to a load. The output power signal provides power to the load. An amount of power provided to the load is based on the duty cycle of the output power signal. In addition, the method includes adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.

Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi–mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj.

Abstract: Prefixes terminating with end node entries each containing identical length prefix portions in a single child table are compressed by replacing the end node entries with one or more compressed single length (CSL) prefix entries in the child table that contain a bitmap for the prefix portions for the end node entries. A different type parent table trie node entry is created for the child table. Where the prefix portions are of non-zero length, the parent table contains a bitmap indexing the end node entries. Where the prefix portions are of length zero, the parent table may optionally contain a bitmap for the prefix portions, serving as an end node. The number of prefix portions consolidated within the CSL node entry is based upon the prefix portion length.

Abstract: A static frequency divider circuit includes a first and second latch connected in series and a feedback path. Each of the latches includes a reading branch and a latching branch. The divider circuit further includes an inter-latch circuit that is connected between the latching branch of the first latch and the reading branch of the second latch. The inter-latch circuit is connected so as to reduce the current needs of the latching branches in both the first and second latches.