Abstract: Existing current sense outputs in a power switch can be utilized to output fault diagnosis information. Current sense circuitry that normally drives the current sense output can be disabled, thereby permitting the fault diagnosis information to be output. An existing fault indicator output can be controlled for bidirectional operation, thereby permitting an external controller to control the output of fault diagnosis information on the existing current sense output.

Abstract: A system and method is disclosed for venting pressure from an integrated circuit package that is sealed with a lid. During a surface mount process for mounting a ball grid array integrated circuit package to a circuit board the application of heat (1) weakens the solder that seals a soldered lid, and (2) increases vapor pressure within the integrated circuit package. This may cause the soldered lid to move out of its soldered position. The present invention solves this problem by providing an integrated circuit with a solder mask that has a plurality of solder mask vents that form a plurality of vapor pressure vents through the solder. The vapor pressure vents prevent the occurrence of any increase in vapor pressure that would shift the soldered lid out of its soldered position. An alternate embodiment vents pressure through an epoxy layer that is used to attach a lid by epoxy.

Abstract: An extent record for an extent based data buffer that includes a host pointer that links the extent record to a next host extent record of a host extent record set, and a storage device pointer that links the extent record to a next storage device extent record of a storage device extent record set. Also, a system for transferring data between a host and a storage device that includes a data buffer coupled to the host and the storage device, where memory in the data buffer is divided into one or more extents, an extent table associated with the data buffer, where the extent table includes at least one extent record, an LBA chain table coupled to the host and the extent table, and a track section table coupled to the storage device and the extent table.

Abstract: Circuits and methods for supplying a temporary power supply at a predetermined voltage. A circuit includes a first DC/DC voltage converter that receives an input from a power supply at a first voltage level and generates an output at a second voltage level, higher than the first voltage level. The output is provided to charge a capacitor. A second DC/DC voltage converter has an input connected to the capacitor for drawing power from the capacitor at the second voltage level and generating an output voltage less than the second voltage level. The second DC/DC voltage converter further includes a feedback input that monitors the circuit's output voltage and activates the second DC/DC voltage converter when the output voltage falls below a predetermined threshold.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers.

Abstract: Variations in the actual resistance of a target poly resistor in a semiconductor integrated circuit can be compensated for by using an active circuit that provides a negative resistance in parallel with the target resistor. This produces a tuned resistance that is closer to a desired resistance than is the actual resistance of the target resistor.

Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract: A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline is a number of lanes wide. The processing stages execute instruction bundles, where each instruction bundle has one or more syllables. Each lane is capable of receiving one of the syllables of an instruction bundle. The instruction cache includes a number of cache lines. The instruction issue unit receives fetched cache lines and issues complete instruction bundles toward the execution clusters. The alignment and dispersal circuitry receives the complete instruction bundles from the instruction issue unit and routes each received complete instruction bundle to a correct one of the execution clusters. The complete instruction bundles are routed as a function of at least one address bit associated with each complete instruction bundle.

Abstract: Sensor cells are arranged in an array in an organic semiconductor layer. Row and column select circuitry addresses the cells of the array one cell at a time to determine the presence of an object, such as a fingerprint ridge or valley, contacting or proximate to a sensing surface above each cell. Control circuitry can be provided in a companion silicon chip or in a second layer of organic semiconductor material to communicate with the array and an associated system processor. The array of sensor cells can be fabricated using a flexible polymer substrate that is peeled off and disposed of after contacts have been patterned on the organic semiconductor layer. The organic semiconductor layer can be used with a superimposed reactive interface layer to detect specific chemical substances in a test medium.

Abstract: A power on reset circuit includes a pulse generation circuit that is connected to receive a supply voltage and respond to an initial ramp-up of that supply voltage to generate an output pulse that transitions from a low to a relatively high state tracking the supply voltage ramp-up. The pulse generation circuit further sets a feedback node in an enable state. Responsive to a flip signal received at an input node, the pulse generation circuit then transitions the output pulse from the relatively high state to the low state and sets the feedback node in a disable state. A static current control transistor switch includes a source-drain circuit coupled to the supply voltage and further includes a gate. The gate is connected to the feedback node such that the transistor switch is actuated in response to the feedback node enable state and unactuated in response to the feedback node disable state.

Abstract: A method for providing a leadframeless package structure is provided. The method includes providing a temporary carrier. The temporary carrier is coupled to a metal foil layer with a temporary adhesive layer. An integrated circuit chip is coupled to the metal foil layer. The temporary adhesive layer and the temporary carrier are removed to form the leadframeless package structure after molding.

Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.

Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.

Abstract: A method for improving gain performance of a Viterbi decoder wherein data relating to the best path and a secondary path are stored for the Viterbi decoder. Slicer errors are determined for the best path and the secondary path for current symbols using the stored data and errors for previous symbols are corrected responsive to the determined slicer errors.

Abstract: A high power density transistor structure includes a transistor package capable of housing a high power density transistor. The transistor package has a package insulator and a plurality of transistor leads. Each of the transistor leads has a far end, a near end and a lead periphery. The high power density transistor structure also includes a solder lock located on at least one of the transistor leads. At least a portion of the solder lock is attachable to a printed circuit board (PCB). At least a portion of the lead periphery of each transistor lead is attachable to at least one of: the PCB and the package insulator.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row group share a common local write digit line and the elements in each column group share a common local write bit line. The array further includes at least one global write digit line coupled to the common local write digit lines of plural row groups, and at least one global write bit line coupled to the common local write bit lines of plural column groups.

Abstract: A cell library for designing integrated domino circuits has a first library portion with a plurality of selectable logic circuits having different transistor sizes and/or logic functions for selection according to desired logic function and parametric characteristics. A second library portion includes a plurality of selectable prechargeable driver circuits. Each of the driver circuits is configured to be connectable to an output of a selected one of the logic circuits. The driver circuits also have at least different transistor sizes. Standard FET devices may be constructed to precharge the output node of the selected logic circuit in the design of a domino logic circuit.

Abstract: A flexible Galois Field multiplier is provided which implements multiplication of two elements within a finite field defined by a degree and generator polynomial. One preferred embodiment provides a method for multiplying two elements of a finite field. According to the method, two input operands are mapped into a composite finite field, an initial KOA processing is performed upon the two operands in order to prepare the two operands for a multiplication in the ground field, the multiplication in the ground field is performed through the use of a triangular basis multiplier, and final KOA3 processing and optional modulo reduction processing is performed to produce the result. This design allows rapid redefinition of the degree and generator polynomial used for the ground field and the extension field.

Abstract: An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.