Abstract: An image matching method and system for use with multiple images of a scene captured from different angles. Image matching is performed by identifying a plurality of segments within at least two images, determining an initial disparity values for pixels in the images and then determining initial disparity planes for the segments by fitting a plane to initial disparity values for the segments. A refined disparity plane set is created by iteratively refitting the disparity planes by using various fitting cost functions and weighted linear systems. A labeling of each segment to a disparity plane is made by minimizing a global energy function that includes energy terms for segment to disparity plane matching as well as penalizing disparity plane discontinuities between adjacent image segments.

Abstract: In one embodiment, a device includes but is not limited to: a first integrated circuit affixed to a substrate; an electronic circuit component affixed to the substrate; a first encapsulation structure encasing the first integrated circuit; a second integrated circuit affixed to the first encapsulation structure; and a second encapsulation structure which at least partially encases the first encapsulation structure, the first integrated circuit, and the electronic component.

Abstract: A self test for a counter system in an integrated circuit includes a clock coupled to counters in a plurality of counters. A first counter in the plurality of counters has a first counter output and a first counter rollover. A second counter in the plurality of counters has a second counter output, a second counter rollover less than the first counter rollover, and a second counter rollover signal that is active when the second counter has rolled over. A comparison circuit having inputs coupled to the first and second counter outputs, compares the first and second counter outputs to produce a counter error output signal. A latch latches the counter error output signal in response to the second counter rollover signal being inactive and the counter error output signal indicating a difference in the first and second counter outputs. Counters may be segmented to reduce a number of digits.

Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit includes switching circuitry connected between the terminals of the write head and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry that generates control signals for controlling the switching circuitry.

Abstract: A method of finding motion vectors for use in MPEG video encoding comprises generating, from a full frame, (i) a first scaled frame having a reduced number of pixels as compared to the full frame and (ii) a second scaled frame having a reduced number of pixels as compared to the first scaled frame. A first, full, best match search is of the second scaled frame is performed to identify rough motion vectors. A second best match search is performed using the rough motion vectors identified by the first search within a limited range in the X and Y directions for each macroblock of the first scaled frame to identify intermediate motion vectors. Finally, a third best match search is performed using the intermediate motion vectors identified by the second search, within a limited range in the X and Y directions for each macroblock of the full frame to identify final motion vectors.

Abstract: A voltage regulator includes an output node and first and second regulator circuits. The first regulator circuit generates a first regulated voltage on the output node when a supply voltage equals or exceeds a predetermined threshold, and the second regulator circuit generates a second regulated voltage on the output node when the supply voltage is less than the predetermined threshold.

Abstract: An integrated circuit for a smart card may include at least one data terminal for providing communications with a host device and a processor for providing an attachment signal on the at least one data terminal for recognition by the host device. Further, the processor may also cooperate with the host device to perform an enumeration based upon at least one default descriptor. In addition, based upon a system event, the processor may selectively remove the attachment signal from the at least one data terminal and thereafter again provide the attachment signal on the at least one data terminal and cooperate with the host device to perform a new enumeration based upon at least one alternate descriptor.

Abstract: An integrated circuit for a smart card may include a plurality of data buffers and a processor. In particular, the processor may selectively allocate data buffers from the plurality thereof and exchange data therewith based upon different types of data. As such, the processor may advantageously change the allocation of the buffers for different data types based upon various bandwidth constraints in a particular smart card environment to enhance bandwidth utilization. By way of example, each type of data may correspond to one of a plurality of endpoints supported by the processor.

Abstract: An integrated circuit for a smart card may include a transceiver and a processor for communicating with a host device via the transceiver and performing a plurality of smart card applications. Moreover, the processor may cooperate with the host device to perform an enumeration based upon at least one default descriptor, and generate a look-up table for allocating data to respective smart card applications based upon the enumeration. Furthermore, the processor may also detect a system event and, responsive to the system event, cooperate with the host device to perform a new enumeration based upon at least one alternate descriptor and generate a new look-up table based thereon.

Abstract: An integrated circuit for a smart card may include a transceiver and a processor for communicating with a host device via the transceiver. More particularly, the processor may provide at least one default descriptor to the host device, and cooperate with the host device to perform an enumeration based upon the at least one default descriptor. Moreover, the processor may also detect a system event and, responsive to the system event, provide at least one alternate descriptor to the host device and cooperate with the host device to perform a new enumeration based thereon.

Abstract: A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit with isochronous processing delay is a One Hot Residue Number System arithmetic processing circuit. The data processing circuit processes the input data while the Req input propagates through a delay circuit that has substantially the same processing delay as the data processing circuit. Thus, the propagation delay of the Req signal is substantially equal to the data processing circuit's processing time. This allows the output of the delay circuit to be used to both latch the output of the data processing circuit and provide a “data ready” output.

Abstract: The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome.

Abstract: A method for synthesizing a domino logic circuit design (18) from a source circuit definition (14) using a static logic circuit synthesis tool (12) includes generating a preliminary domino logic circuit (26) design using the circuit synthesis tool (12) and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design (30).

Abstract: A method and system of scaling images on a video display is disclosed. A video data stream is processed into video data, which is displayed on a video display at a predetermined aspect ratio. A user manipulable controller, such as a joystick, is operative with a graphics processor unit for scaling images on the video display by obtaining video source values of pixel width and height to be displayed and determining the smallest integer increment on the x/y axis that will maintain the desired aspect ratio using a greatest common denominator to reduce the ratio to the lowest integer.

Abstract: An amplifier may include an output stage including first and second output transistors, and a biasing stage for generating first and second biasing voltages at control terminals of the first and second output transistors, respectively, based upon a supply voltage and an input signal of the amplifier. The amplifier may also include a clamping stage having first and second clamping transistors for clamping outputs of the first and second output transistors to upper and lower clamping voltages, respectively. Additionally, the amplifier may also advantageously include a saturation detector connected to the clamping stage for providing a saturation signal for at least one of (a) the output of the first output transistor being clamped to the upper clamping voltage, and (b) the output of the second output transistor being clamped to the lower clamping voltage.

Abstract: A microlens of an inorganic material having a relatively high index of refraction is formed with a convex lower surface for refracting light from above through an underlying spacer layer to converge on a photodiode therebelow. The microlens and photodiode may be replicated in an array of such elements along with color filters and CMOS circuit elements on a semiconductor chip to provide an image sensor. The spacer layer, which has a relatively low refractive index, is subjected to a selective isotropic etch through an opening in an etch mask to define a concave surface that forms an interface with the convex lower surface of the microlens upon subsequent conformal deposition of the material of the microlens.

Abstract: A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits a form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.

Abstract: The present invention provides a system, method and an apparatus for a digital video processor comprising an error memory and a merge memory, a half pixel filter communicably coupled to the merge memory, a controller communicably coupled to the error memory, the merge memory and the half pixel filter. The present invention also including a sum unit communicably coupled to the error memory. The controller executing one or more instructions to provide motion compensation during video decoding.

Abstract: An integrated circuit is used in a smart card device and includes at least one memory for storing mass storage data. The smart card device communicates through a chip/smart card interface (CCID) in accordance with the International Standards Organization 7816 (ISO 7816) protocol and a mass storage interface. A microprocessor is connected to the at least one memory and operative for initiating communications with the host using a CCID interface and transferring mass storage data using a mass storage interface.

Abstract: A load transient compensator and method of operating the load transient compensator for reducing the transient response time to a load capable of operating at either of several consumption levels when the load changes its power consumption level . The load transient compensator has a comparator having an output connected to an input of an upper driver and of a lower driver with the output of each of the driver being connected to a gate of a power transistor. When the load is in sleep mode and is about to start being accessed, the upper driver is turned on to turn on its associated transistor to supply additional current to the load, regulated by the comparison circuit. When the load is in the power up mode and it is about to stop being accessed, the lower driver is turned on to turn on its associated transistor to drain current supplied to the load by a supply, regulated by the comparison circuit.