Patents Assigned to STMicroelectronics, Inc.
  • Constant voltage discharge device
    Patent number: 7098557
    Abstract: Circuits and methods for supplying a temporary power supply at a predetermined voltage are disclosed. A circuit includes first DC/DC voltage that receives an input from a power supply at a first voltage level and generates an output at a second voltage level, higher than the first voltage level. The output is provided to charge a capacitor. A second DC/DC voltage converter has an input connected to the capacitor for drawing power from the capacitor at the second voltage level and an generates an output voltage less than the second voltage level. The second DC/DC voltage converter further includes a feedback input that monitors the circuit's output voltage and activates the second DC/DC voltage converter when the output voltage falls below a predetermined threshold.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: August 29, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Cal Swanson, Vincent Himpe
  • Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes
    Patent number: 7099881
    Abstract: Sparsely distributed prefixes within a bitmapped multi-bit trie are compressed by one or more of: replacing a single entry table string terminating with a single prefix end node with a parent table entry explicitly encoding a prefix portion; replacing a table with only two end nodes or only an end node and an internal node with a single parent table entry explicitly encoding prefix portions; replacing two end nodes with a single compressed child entry at a table location normally occupied by an internal node and explicitly encoding prefix portions; and replacing a plurality of end nodes with a prefix-only entry located at the table end explicitly encoding portions of a plurality of prefixes. The compressed child entry and the prefix-only entry, if present, are read by default each time the table is searched. Run length encoding allows variable length prefix portions to be encoded.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: August 29, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicholas Julian Richardson, Suresh Rajgopal, Lun Bin Huang
  • Preamplifier circuit and method for a disk drive device
    Patent number: 7099098
    Abstract: An amplifying circuit and method are disclosed for amplifying electrical signals, such as electrical signals generated by the read head of a disk drive. The circuit includes a pair of cross-coupled differential amplifier circuits. Each differential amplifier circuit is asymmetric, including two input transistors of different transistor types. For instance, a first of the two input transistors of each differential amplifier circuit may be a bipolar transistor and a second of the two input transistors may be a field effect transistor. By utilizing asymmetric differential amplifier circuits, a relatively wider operating frequency range is obtained.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: August 29, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Baris Posat, Kemal Ozanoglu, Alessandro Venca
  • Buffer-less de-skewing for symbol combination in a CDMA demodulator
    Patent number: 7099293
    Abstract: A demodulator in a wireless communication network for combining symbols without the need to store the received symbols in buffers for subsequent retrieval and accumulation. The demodulator includes a plurality of accumulators capable of accumulating received symbols, each symbol associated with a physical channel and a propagation path. The demodulator includes a multiplexer for routing the received symbols to an appropriate accumulator selected from the plurality of accumulators. The symbols received from different propagation paths are each routed and accumulated to an appropriate accumulator based on a physical channel of the received symbol and a value of an indicator associated with a propagation path of the received symbol.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: August 29, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: Stefano Cervini
  • Method for providing a redistribution metal layer in an integrated circuit
    Patent number: 7096581
    Abstract: An integrated circuit includes a portion having at least one active circuit area. The integrated circuit also includes a redistribution metal layer fabricated at least partially during fabrication of the portion of the integrated circuit. A method for fabricating an integrated circuit includes fabricating a portion of the integrated circuit, where the portion includes at least one active circuit area. The method also includes fabricating a redistribution metal layer at least partially during fabrication of the portion of the integrated circuit.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: August 29, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Danielle A. Thomas, Harry Michael Siegel, Antonio A. Do Bento Vieira, Anthony M. Chiu
  • Integrated lid formed on MEMS device
    Patent number: 7098065
    Abstract: An integrated lid for microelectromechanical system (MEMS) devices is formed from a nitride layer deposited over a cavity containing movable parts for the device. Pillars are formed through openings within large area movable parts to support the lid over those parts. Slides are formed and moved under large etchant openings through the lid to allow the openings to be sealed by sputtering.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: August 29, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Anthony M. Chiu, Harry Michael Siegel
  • System and method for interfacing network station subsystems
    Patent number: 7096252
    Abstract: A network station subsystem architecture that uses a simplified interface reference discovery method and system is provided. In one embodiment a method for managing client-server communications is disclosed that includes providing a server with functions and interface methods; providing a client with references to the interface methods; and processing client requests by invoking the interface methods on the server via the references. Ideally, the interface methods are implemented by providing the server with a table of pointers to the functions, and providing the client with references to the table of pointers, ideally at the time of design. In another embodiment, a system for managing communications in a network station for a data-over-cable network having a plurality of network stations is provided.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: August 22, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Harry Hvostov, Anthony Fung
  • Fluorescent lamp assembly having multiple settings and method
    Publication number: 20060181225
    Abstract: A fluorescent lamp assembly includes a fluorescent lamp ballast capable of detecting at least one of a plurality of input signals and generating an output signal. The output signal is associated with a power level that is based on the at least one detected input signal. The fluorescent lamp assembly also includes a fluorescent lamp capable of receiving the output signal and generating light. An intensity of the light is based on the power level associated with the output signal.
    Type: Application
    Filed: February 17, 2005
    Publication date: August 17, 2006
    Applicant: STMicroelectronics, Inc.
    Inventor: Thomas Hopkins
  • Bypass circuitry for use in a pipelined processor
    Patent number: 7093107
    Abstract: There is disclosed a data processor that uses bypass circuitry to transfer result data from late pipeline stages to earlier pipeline stages in an efficient manner and with a minimum amount of wiring. The data processor comprises: 1) an instruction execution pipeline comprising a) a read stage; b) a write stage; and c) a first execution stage comprising E execution units that produce data results from data operands.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: August 15, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: Anthony X. Jarvis
  • Content addressable memory circuit with improved memory cell stability
    Publication number: 20060171183
    Abstract: A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.
    Type: Application
    Filed: February 1, 2005
    Publication date: August 3, 2006
    Applicant: STMicroelectronics, Inc.
    Inventors: Mark Lysinger, Francois Jacquet, Phillippe Roche
  • Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same
    Patent number: 7084464
    Abstract: A cell library for designing integrated domino circuits has a first library portion with a plurality of selectable logic circuits having different transistor sizes and/or logic functions for selection according to desired logic function and parametric characteristics. A second library portion includes a plurality of selectable prechargeable driver circuits. Each of the driver circuits is configured to be connectable to an output of a selected one of the logic circuits. The driver circuits also have at least different transistor sizes. Standard FET devices may be constructed to precharge the output node of the selected logic circuit in the design of a domino logic circuit.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: August 1, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: Thomas David Zounes
  • Electronic device including motion sensitive power switching integrated circuit and related methods
    Patent number: 7084762
    Abstract: An electronic device includes a motion sensitive power switching integrated circuit, which, in turn, includes a power switch connected between an input and an output, and a MEMS inertial sensing switch movable from a first position to a second position based upon motion thereof. The motion sensitive power switching integrated circuit also includes a detector operating the power switch to supply power to the output from the input based upon the MEMS inertial sensing switch moving from the first position to the second position. The first and second positions may be, respectively, a normally open position and a closed position. The device may be unpowered until the MEMS inertial sensing switch moves from the open to the closed position. The detector may generate a power on reset (POR) signal based upon the MEMS inertial sensing switch moving from the open to the closed position.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: August 1, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Giorgio Pedrazzini, Ernesto Lasalandra, Bendetto Vigna
  • Enhanced resolution video construction method and apparatus
    Patent number: 7085323
    Abstract: Enhanced resolution video sequence results from construction of enhanced resolution key frames and synthesis of enhanced resolution non-key frames. Key frames are constructed by processing a plurality of initial resolution frames in order to produce the enhanced resolution image components of the key frame. Non-key frames are synthesized using the enhanced resolution image component of the key frames and image component motion determinations from initial resolution frames using an image warping technique. Non-key frame image components are further improved by blending and error correction processes.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: August 1, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: Li Hong
  • Clock distribution providing optimal delay
    Patent number: 7084688
    Abstract: The invention provides a clock delay arrangement accounting for the worst-case delay situation of data signals, which is independent of the layout and technology. It comprises a main clock line; two dummy clock lines, each arranged parallel to the main clock line, and the main clock line disposed between the two dummy clock lines; and a clock source coupled to the main clock line and the two dummy clock lines, adapted to drive said dummy clock lines in phase opposition with respect to the main clock line.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: August 1, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: David McClure
  • Variable boost voltage row driver circuit and method, and memory device and system including same
    Patent number: 7085190
    Abstract: A row driver circuit receives a supply voltage and operates to develop a boosted voltage having a magnitude that is equal to the sum of an incremental boost voltage and a magnitude of the supply voltage. The magnitude of the incremental boost voltage is a function of the magnitude of the supply voltage to maintain the boosted voltage at an approximately constant value independent of variations in the supply voltage. A method of generating a boosted voltage includes detecting a value of a supply voltage, generating an incremental boost voltage having a value that is a function of the detected supply voltage, and adding the generated incremental boost voltage to the supply voltage to generate the boosted voltage.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: August 1, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: James Leon Worley, James Brady
  • Spatio-temporal graph-segmentation encoding for multiple video streams
    Publication number: 20060165169
    Abstract: A multiple video stream capture and encoding apparatus produces compressed data that represents multiple video streams capturing a common scene. Inages from multiple video streams are analyzed to identify image color segments that are encoded into a composite graph data structure. Corresponding image segments across the multiple video streams are also identified and represented by one node in the composite graph data structure. The composite graph data structure also includes links between pairs of nodes that describe the relationship between the image segments associated with those nodes. The composite graph data structure is updated to represent changes to the image segments in the multiple video streams over time. The composite graph data structure is used to create compressed encoded data for storage and/or transmission.
    Type: Application
    Filed: January 21, 2005
    Publication date: July 27, 2006
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Kim Ng, Clifford Stein, Huisheng Wang
  • Smart card including a JTAG test controller and related methods
    Patent number: 7080789
    Abstract: An integrated circuit for a smart card may include a transceiver for communicating with a host device and a Joint Test Action Group (JTAG) test controller for performing at least one test operation. Further, the integrated circuit may also include a processor for causing the JTAG test controller to initiate the at least one test operation based upon receiving at least one test request from the host device via the transceiver. More particularly, the processor may convert the at least one test request to JTAG data for the JTAG test controller. That is, the integrated circuit advantageously allows communications between the host device and the JTAG controller via a system bus, for example, without the need for a dedicated JTAG test access port (TAP) which is typically required for accessing JTAG controllers.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: July 25, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: Taylor J. Leaming
  • Method and apparatus using a two-dimensional circular data buffer for scrollable image display
    Patent number: 7079160
    Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed linear data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. New data is loaded into the buffer as the displayed data approaches the edge of the buffered data.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: July 18, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: Osvaldo M. Colavin
  • Circuit and method for controlling the parking and unparking of a read-write head
    Patent number: 7079350
    Abstract: A control circuit controls a motor assembly having a coil and a movable arm. The control circuit includes a drive circuit that is coupled to the coil and that generates a drive signal in response to a control signal and a speed signal. The control circuit also includes a sensor circuit that is coupled to the drive circuit and to the coil and that generates the speed signal at a level that corresponds to the speed of the arm. In a disk drive, such a circuit can be used to control the movement of a read-write-head assembly during parking and unparking of a read-write head. The circuit monitors the speed of the head and uses this speed information as feedback to maintain the speed of the head within a specified range. This prevents damage to the head and other disk-drive components, particularly in a disk drive that incorporates a head parking platform.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: July 18, 2006
    Assignee: STMicroelectronics, Inc.
    Inventors: Carlo Vertemara, Paolo Menegoli, Giorgio Pedrazzini
  • Magnetic random access memory element
    Patent number: 7079415
    Abstract: A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: July 18, 2006
    Assignee: STMicroelectronics, Inc.
    Inventor: Christophe Frey