Abstract: Counter-clockwise and clockwise quadrant transitions are detected and accumulated with respect to a received complex signal over a certain time period. These transitions may then be compared in order to obtain information indicative of both a magnitude and phase of a frequency offset error. Additionally, zero-crossings of the received complex signal over the same certain time period are detected and accumulated. The accumulated crossings provide information indicative of frequency offset magnitude. The determined magnitude and phase of the frequency offset error may then be used to adjust a local oscillator frequency to provide for improved receiver performance.

Abstract: A method and ethernet device is disclosed and includes an extended FIFO buffer. The link partner within the ethernet system is in communication with data terminal equipment (DTE). The speed of the link partner determined using a first packet received within the FIFO buffer. Subsequent FIFO buffer reading is optimized based on the determined speed of the link partner, thus for enhancing the inter-packet gap space usage.

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract: A method for determining a rotor position in a DC motor having a plurality of windings, including a rotor winding and a plurality of stator windings begins with producing a changing current flow in a pulsed winding to induce a response signal in other windings of the motor. The pulsed winding may be the rotor winding or selected ones of the stator windings. If the pulsed winding is the rotor winding, response signals induced in at least two of the stator windings are analyzed compute the rotor position. If the pulsed winding is the stator winding, response signals induced from pulsing at least two stator windings are sensed in the rotor winding and analyzed compute the rotor position. A system for computing a rotor position may include comparators for comparing induced response signals in stator windings.

Abstract: A released-beam sensor includes a semiconductor substrate having a layer formed thereon, and an aperture formed in the layer. A beam is mechanically coupled at a first end to the layer and suspended above the layer such that a second end forms a cantilever above the aperture. A boss is coupled to a second end of the beam and suspended at least partially within the aperture. The beam is configured to flex in response to acceleration of the substrate along a vector substantially perpendicular to a surface of the substrate. Parameters of the sensor, such as the dimensions of the beam, the mass of the boss, and the distance between the boss and a contact surface within the aperture, are selected to establish an acceleration threshold at which the boss will make contact with the contact surface. The sensor may be employed to deploy an airbag in a vehicle.

Abstract: An acceleration sensor includes a semiconductor substrate, a first layer formed on the substrate, a first aperture within the first layer, and a beam coupled at a first end to the substrate and suspended above the first layer for a portion of the length thereof. The beam includes a first boss coupled to a lower surface thereof and suspended within the first aperture, and a second boss coupled to an upper surface of the second end of the beam. A second layer is positioned on the first layer over the beam and includes a second aperture within which the second boss is suspended by the beam. Contact surfaces are positioned within the apertures such that acceleration of the substrate exceeding a selected threshold in either direction along a selected axis will cause the beam to flex counter to the direction of acceleration and make contact through one of the bosses with one of the contact surfaces.

Abstract: A subpixel interpolator includes an input memory capable of storing video information formed from full pixels. The subpixel interpolator also includes at least one interpolation unit capable of performing subpixel interpolation to generate half-pixels and quarter-pixels in parallel. Multiple half-pixels and multiple quarter-pixels are generated concurrently during the subpixel interpolation. In addition, the subpixel interpolator includes an output memory capable of storing at least some of the full pixels, half-pixels, and quarter-pixels. In some embodiments, the at least one interpolation unit includes a horizontal half-pixel interpolation unit, two vertical half-pixel interpolation units, and a quarter-pixel interpolation unit, all of which may operate in parallel. In particular embodiments, the interpolation units are formed from adders and shifters and do not include any multipliers.

Abstract: A regulator circuit and method are disclosed for a system. The regulator circuit may include a compare circuit for comparing a first supply voltage to a predetermined voltage level and generating an enable signal based upon the comparison. A selectively enabled voltage regulator is adapted to make available a predetermined current level at a regulated voltage when enabled by the compare circuit. When disabled, the voltage regulator circuit is prohibited from providing current. The voltage regulator may include an output transistor that is normally biased in a saturation mode of operation and is deactivated by the enable signal. By controlling the output transistor based upon the output of the compare circuit, the need for a relatively large transistor for connecting to the first supply voltage is eliminated.

Abstract: A method for storing a plurality of still images to form a panoramic image. The method comprising the steps of receiving a first image forming a part of a series of images to form a panoramic image and storing the first image in memory. When one or more subsequent images after the first image are received the steps of calculating one or more panoramic parameters between a current image and a previous image stored in memory and storing the current image with the one or more panoramic parameters in memory are performed.

Abstract: A processor includes a multi-stage pipeline having a plurality of stages. Each stage is capable of receiving input values and providing output values. Each stage performs one of a plurality of data transformations using the input values to produce the output values. The data transformations collectively approximate at least one of: a discrete cosine transform and an inverse discrete cosine transform. The stages do not use any multipliers to perform the data transformations.

Abstract: The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes. The method includes applying a configuration signal on one of the first and second signal nodes and configuring the buffer responsive to the applied configuration signal.

Abstract: In a packaged integrated circuit, electrostatic discharge protection is provided by portions of a lead frame on which the integrated circuit is mounted. The lead frame includes a die paddle on which an integrated circuit die is mounted, with plastic or epoxy material encapsulating exposed surfaces of the integrated circuit die except for a sensing surface, and supporting pins or leads formed from the lead frame. Portions of the lead frame extending from the die paddle are folded around sides of the encapsulated integrated circuit die and over, or adjacent to and level with, a peripheral upper surface of the encapsulated integrated circuit die to form an electrostatic discharge ring. The lead frame portions folded around the integrated circuit package are connected to ground through a ground pin, so that charge on a human finger touching the electrostatic discharge ring is dissipated to ground before the finger contacts a sensing surface of the integrated circuit.

Abstract: The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Abstract: A servo control circuit provides seamless transition between seek and track modes while enabling both rapid seek mode operation and accurate tracking. The control circuit includes an analog-to-digital converter having a non-linear characteristic. The non-linear characteristic provides disproportionately large control voltages to derive speed and settling in the seek mode and essentially linear control voltages in the track mode to provide low noise and accurate tracking operation.

Abstract: A system tests an integrated circuit at operational speed. The system includes a high frequency clock converter that receives test clock signals at a speed lower than operational speed of the integrated circuit to be tested. The high frequency clock converter generates test clock signals for operational speed testing of the integrated circuit.

Abstract: A voltage regulator includes first and second transistors arranged in parallel and configured to regulate current flow to an output node, and a sensing circuit configured to sense a voltage level at the output node and provide a signal proportional thereto the regulator also includes a control circuit configured to receive the signal from the sensing circuit and provide control signals at control terminals of the first and second transistors such that voltage at the output node is maintained substantially at a selected level. The control circuit further configured to hold the second transistor in an off state while a demand for current at the output node remains below an output threshold. The second transistor is configured to control a large portion of load current above the output threshold. The regulator may also include a current bypass circuit configured to shunt leakage current of the second transistor to ground, away from the sensing circuit.

Abstract: A method for estimating the speed of a mobile device in a network is provided that includes selecting a correlation length from a plurality of possible correlation lengths. A correlation result is generated based on the selected correlation length. A speed estimate is generated for the mobile device based on the correlation result.

Abstract: An image processing system which processes, in real time, multiple images, which are different views of the same object, of video data in order to match features in the images to support 3 dimensional motion picture production. The different images are captured by multiple cameras, processed by digital processing equipment to identify features and perform preliminary, two-view feature matching. The image data and matched feature point definitions are communicated to an adjacent camera to support at least two image matching. The matched feature point data are then transferred to a central computer, which performs a multiple-view correspondence between all of the images.

Abstract: A dynamic random access memory (DRAM) includes a bit line pair, including a first bit line and a second bit line. Memory cells and a sense amplifier are coupled to the bit lines. A first characterization cell is coupled between the first bit line and a first reference supply line. The first characterization cell includes a capacitor. Similarly, a second characterization cell is coupled between the first bit line and the first reference supply line. The second characterization cell also includes a capacitor but preferably with a different capacitance. In the preferred embodiment, similar characterization cells are coupled to the second bit line.

Abstract: A hybrid circuit is disclosed for effectively communicating information over a telecommunications line to which a transmitter and receiver are connected. The hybrid circuit is configured as a filter for filtering at the receiver input signals at predetermined frequencies appearing on the transmitter output and the telecommunications line. The filter circuit additionally forms a capacitive divider for scaling signals appearing at the transmitter output and canceling the scaled signals at the receiver input with related signals appearing on the telecommunications line. In one embodiment of the present invention for communicating using the ADSL protocol, the filter circuit is a first order high pass filter.