Abstract: An emulator for a multi-mode smart card may include emulation circuitry for performing smart card applications in a plurality of operational modes. The emulator may also include a smart card connector to be connected to a smart card adapter operable in at least one of the plurality of operational modes. The smart card connector may include a plurality of contacts. Moreover, the emulator may further include a plurality of cable assemblies having first ends connected to the emulation circuitry, where each cable assembly is for a respective operational mode. Further, the emulator may also include an interface device connected between second ends of the plurality of cable assemblies and the smart card connector for selectively electrically connecting a selected cable assembly to predetermined ones of the contacts of the smart card connector based upon the at least one operational mode of the smart card adapter.

Abstract: A system of the present invention tests the design of a universal serial bus (USB) smartcard device and includes a bus analyzer for running test cases to generate USB bus traffic. A processor is operatively connected to the bus analyzer for receiving and transforming data about USB traffic into a selected data format that is usable across different smartcard development environments.

Abstract: There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.

Abstract: A method of fabricating an integrated circuit sensor package. The method comprises the steps of: 1) mounting a substrate on a first mold block, the substrate comprising a substantially planar material having a first substrate surface and a second substrate surface that contacts a mounting surface of the first mold block; 2) placing an adhesive on the first substrate surface; 3) placing an integrated circuit sensor on the adhesive; and 4) pressing a second mold block against the first substrate surface. The second mold block comprising a cavity portion for receiving the integrated circuit sensor, a contact surface surrounding the cavity portion, and a compliant layer mounted with the cavity portion. Pressing the second mold block against the first substrate surface causes the contact surface to form with the first substrate surface a seal surrounding the integrated circuit sensor.

Abstract: An emulator for a smart card device and associated method have at least two virtual components as functional blocks for a smart card device and operative in different clock domains. A functional buffering block is operative for communicating with the functional blocks and buffering between the functional blocks and allowing emulation.

Abstract: A servo control circuit provides seamless transition between seek and track modes while enabling both rapid seek mode operation and accurate tracking. The control circuit includes an analog-to-digital converter having a non-linear characteristic. The non-linear characteristic provides disproportionately large control voltages to derive speed and settling in the seek mode and essentially linear control voltages in the track mode to provide low noise and accurate tracking operation.

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal.

Abstract: A method, system and computer readable medium for transforming three dimensional (3D) color information into a color standard is described. A 3D cube defined by eight RGB color points representing the eight vertices of the 3D cube is stored. Each of the eight points represents one of the colors: red, yellow, white, magenta, blue, black, green and cyan. In addition, each of the eight points represents the difference between the capacity of a display and the color standard. The 3D cube is divided into six tetrahedrons and the tetrahedron corresponding to an input RGB pixel is selected. A 3×3 matrix based on the vertices of the selected tetrahedron is calculated. The 3×3 matrix is then multiplied by the components of the input RGB pixel to produce an output RGB pixel conforming to the color standard.

Abstract: An electronic circuit includes a selectively configurable differential signal interface and a selection control input for selecting one of a plurality of standard differential signal interfaces for configuration of the differential signal interface. The selection control input selects one of the following plurality of standard differential signal interfaces: reduced swing differential signaling (RSDS), low voltage differential signaling (LVDS), mini low voltage differential signaling (mini-LVDS), and bussed low voltage differential signaling (BLVDS), for configuration of the differential signal interface. The electronic circuit may also include a plurality of selectable voltage sources (611, 612, 613) and a plurality of selectable current sources (614, 615, 616, 617), for selecting, in response to an input signal at the selection control input, at least one of an operating D.C. voltage, a standard differential signal voltage, and a standard differential signal current for the differential signal interface.

Abstract: A sense amplifier circuit for a memory cell includes a sense amplifier that is operable to be coupled to a memory cell via data lines, and including read bus complement and read bus true lines operative with a data output through which a data output signal is passed. An equalization circuit and enable circuit are operable with the sense amplifier. A control circuit is operable for disconnecting the data output from preferably the one of the read bus complement line and minimize unwanted transitions on the data output signal.

Abstract: A thick metal layer is formed on a semiconductor integrated circuit in multiple different deposition chambers. A first portion of the metal layer is formed in a first deposition chamber, the first thickness being approximately half the target thickness. The substrate is then removed from the first chamber and transported to a second chamber. The deposition of the same metal layer continues in a second chamber, having the same grain structure and orientation. The second portion of the metal layer is grown to achieve the final thickness. By using two different deposition chambers to form the single metal layer, layers in excess of 25,000 angstroms in thickness can be obtained.

Abstract: The bottom mold portion for a transfer molding system is covered with a deformable material. During mold clamping, the deformable material contacts the bottom surface of the packaging substrate on which the integrated circuit die is mounted. Deformation of this relatively soft covering on the bottom mold portion accommodates thickness variations in the packaging substrate, as well as non-planarity of the adhesive layer between the integrated circuit die and packaging substrate in exposed active area integrated circuits.

Abstract: A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module receives the sum output of a first of the plurality of full adders and a carry output of a second of the plurality of full adders and provides an exclusive-OR output. An AND logic module has a plurality of inputs and an AND output, wherein the exclusive-OR output is electrically connected to one of the plurality of inputs of the AND logic module, and the AND output provides a signal that indicates whether the first data equals the sum of the second data and third data.

Abstract: In linear arrays of charge coupled device photosensors, sensor integrated circuits are contained in surface mountable packaging allowing individual segments to be soldered into place within the array. For solder-mountable packaging, unencapsulated sensor circuits are mounted onto a lead frame strip with the space between the circuits equaling the width of a singulation saw. After die mounting and wire bonding, a continuous strip of plastic or resin molding covers the wire bonds on one side and the edge of the silicon on the other, protecting the lead frame strip and other parts, leaving the active sensor area exposed. The lead frame is then trimmed and formed in a conventional manner, and the packaged sensor circuits are separated with a singulation saw cutting between the circuits. The resulting self-contained device may then be surface mounted within a linear array with solder rather than depending on Chip On Board technology.

Abstract: An integrated circuit (IC) may include at least one smart card memory for storing a set of default requests and at least one alternate request for each default request. The IC may further include a microprocessor connected to the at least one smart card memory for communicating with a host device using the default requests and alternate requests. The microprocessor may selectively switch between using the default requests and the alternate requests when communicating with the host device. As such, this provides a “moving target” which makes it difficult for would-be hackers to determine which requests are used for which smart card operations and, thus, to decipher and interfere with data communications.

Abstract: An integrated circuit for a smart card may include a transceiver for communicating with a host device and a Joint Test Action Group (JTAG) test controller for performing at least one test operation. Further, the integrated circuit may also include a processor for causing the JTAG test controller to initiate the at least one test operation based upon receiving at least one test request from the host device via the transceiver. More particularly, the processor may convert the at least one test request to JTAG data for the JTAG test controller. That is, the integrated circuit advantageously allows communications between the host device and the JTAG controller via a system bus, for example, without the need for a dedicated JTAG test access port (TAP) which is typically required for accessing JTAG controllers.

Abstract: A method and circuit are disclosed for an integrated circuit having one or more memory cells, each memory cell including first and second p-channel transistor and first and second n-channel transistors configured as cross-coupled logic inverters between first and second reference voltage levels during a normal mode of operation. Power control circuitry is coupled to a source terminal of the first p-channel transistor of each memory cell for providing to the first p-channel transistors the first reference voltage level during the normal mode of operation. This causes a first voltage less than the first reference voltage level to appear at the source terminal of the first p-channel transistors during a data corruption mode of operation wherein data stored in the one or more memory cells is corrupted.

Abstract: A memory cell includes first and second p-channel transistors and first and second n-channel transistors in a cross-coupled latch configuration. Power control circuitry associated with the memory cell is coupled to selectively perform voltage transitions on the source terminals of one or more of the n-channel and/or p-channel transistors in the memory cell during a data corruption mode of operation to destroy data stored in the latch and set the memory cell to a known state. In one implementation, the power control circuitry is coupled to the source terminal of one of the n-channel transistors to transition that terminal from a low voltage reference level (present during a normal mode of operation) to a high voltage reference level and back to the low voltage reference level. In another implementation, the power control circuitry is coupled to the source terminal of one of the n-channel transistors and the source terminal of at least one of the p-channel transistors.

Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract: An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.