Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.

Abstract: A method and circuit are disclosed for mirroring current. The circuit includes a reference branch through which a first current flows, and at least one mirror branch through which a second current flows that is proportional to the first current. The circuit further includes a current amplifier having an input coupled, via a capacitor, to the reference branch and an output coupled to one of the reference branch and the at least one mirror branch. The current amplifier provides, at relatively high frequencies, a current to the circuit that substantially compensates for current passing through a parasitic capacitance appearing in the circuit.

Abstract: A sense amplifier for use in memory devices. The sense amplifier may include a pair of cross-coupled inverters, each inverter including at least two transistors. The sense amplifier may further include a first capacitor coupled to a first input/output terminal of the sense amplifier and a second capacitor coupled to a second input/output terminal thereof. A change in voltage differential appearing across the input/output terminals bootstraps the cross-coupled inverters to facilitate activation and deactivation of the transistors in the cross-coupled inverters. Consequently, response time of the sense amplifier is reduced.

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A smart card includes a card body and integrated circuit carried by the card body. A microprocessor communicates with a host when the smart card is inserted within a smart card reader. The integrated circuit is operative for driving at least one multi-color light emitting diode (LED) indicative of smart card transactions between the smart card and a USB port of the host and operative for modulating the multi-color LED based on operational attributes of the smart card and/or transactions between the smart card and USB port of the host.

Abstract: An asymmetrical polysilicon thin film transistor is formed above a gate electrode on a semiconductor substrate. The transistor is separated from the gate electrode by a gate oxide layer, and includes a channel region immediately above the gate electrode. Highly doped source/drain regions are formed within the polysilicon on either side of the channel region. On the drain side of the channel only, a lightly doped drain region is formed between the channel region and the highly doped drain region. The highly doped source region is immediately adjacent the channel region.

Abstract: An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of retired identifiers associated with retired instructions and for determining a next retire ID sequentially following the set; 2) first ID generation circuitry for sequentially assigning identifiers to destination registers associated with instructions entering the pipelines; 3) second ID generation circuitry associated with the first pipeline for identifying a first dependent source register associated with a first dependent source operand of a first instruction entering the first pipeline and assigning an ID of the first register to the first operand; and 4) instruction scheduling circuitry for comparing the first operand ID of the first instruction with the next retire ID and scheduling the first instruction for execution if the first operand ID is less than or equal to the next retire ID.

Abstract: An improved vacuum plasma etching device for plasma etching semiconductor wafers that have a photo-resist pattern. The improved plasma etching device has a reaction chamber in which the plasma etching is performed during a process cycle, an entrance vacuum loadlock for holding the next semiconductor wafer to be plasma etched, an exit vacuum loadlock for transporting the semiconductor wafers out of the reaction chamber after the plasma etching process, and a source of ultraviolet light. Exposing the semiconductor wafer to the ultraviolet light cures the photo-resist patterns, thereby improving CD dispersion, enhancing pattern transfer, and preventing photo-resist reticulation. Curing the photo-resist patterns while the semiconductor wafer is being held during the process cycle in the entrance vacuum loadlock, increases efficiency and productivity.

Abstract: For use in a pipeline network search engine of a router, a path compression optimization system and method is disclosed for eliminating single entry trie tables. The system embeds in a parent trie table (1) path compression patterns that comprise common prefix bits of a data packet and (2) skip counts that indicate the length of the path compression patterns. The network search engine utilizes the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses that are necessary to traverse the data structure.

Abstract: A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first reference voltage signal. A comparator compares the unregulated power supply voltage to the trimmed reference voltage signal and asserts an output signal based upon the comparison. The output signal is fed back as an input to the trim circuit so that the trim circuit provides a hysteresis effect.

Abstract: Sparsely distributed prefixes within a bitmapped multi-bit trie are compressed by: replacing a single entry table string terminating with a single prefix end node with a parent table entry explicitly encoding a prefix portion; replacing a table with only two end nodes or only an end node and an internal node with a single parent table entry explicitly encoding prefix portions; replacing two end nodes with a single compressed child entry at a table location normally occupied by an internal node and explicitly encoding prefix portions; and/or replacing a plurality of end nodes with a prefix-only entry located at the table end explicitly encoding portions of a plurality of prefixes. The compressed child entry and the prefix-only entry, if present, are read by default each time the table is searched. Run length encoded allows variable length prefix portions to be encoded.

Abstract: A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit rather than passing the search results through the remaining pipeline units. Early retirement may be triggered by either the absence of subsequent strides to be processed or completion (a miss or end node match) of the search, together with an absence of active search operations in subsequent pipeline units. The early retirement mechanism may be included in those pipeline units corresponding to a last stride for a maximum prefix length shorter than the pipeline (e.g., 20 or 32 bits rather than 64 bits), in pipeline units selected on some other basis, or in every pipeline unit. Worst-case and/or average latency for prefix search operations is reduced.

Abstract: A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes. The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit. An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks.

Abstract: Prefixes terminating with end node entries each containing identical length prefix portions in a single child table are compressed by replacing the end node entries with one or more compressed single length (CSL) prefix entries in the child table that contain a bitmap for the prefix portions for the end node entries. A different type parent table trie node entry is created for the child table. Where the prefix portions are of non-zero length, the parent table contains a bitmap indexing the end node entries. Where the prefix portions are of length zero, the parent table may optionally contain a bitmap for the prefix portions, serving as an end node. The number of prefix portions consolidated within the CSL node entry is based upon the prefix portion length.

Abstract: A method is provided for determining the actual amplitude of a signal relative to a predetermined amplitude. According to the method, two samples of the signal are squared to produce two squared samples, and the sum of the two squared samples minus the square of the predetermined amplitude is calculated to produce a difference of squares. A shift operation is performed on the difference of squares to determine a difference between the actual amplitude and the predetermined amplitude. In a preferred embodiment, two consecutive samples of the signal are taken at four times the frequency of the signal. Also provided is a circuit device that includes an A/D converter, a variable gain amplifier, and a feedback loop. The A/D converter converts an analog signal into a digital signal, and the variable gain amplifier adjusts the amplitude of the analog signal. The feedback loop controls the variable gain amplifier based on a difference between the amplitude of the analog signal and a predetermined amplitude.

Abstract: A head position control system for a dual stage actuation disk drive system. A feedback system is provided for modifying a primary and a secondary input command signal to produce primary and secondary error signals. A controller receives the primary error signal and transmits primary actuator arm positioning information to the primary actuator. A secondary controller receives the secondary error signal and transmits secondary actuator arm positioning information to the secondary actuator. The feedback system creates a position error signal (PES) using information from servo wedges and runout information and the PES is used to produce the secondary error signal. The feedback system produces a reconstructed error signal including angular position information for the primary actuator arm by processing a back electromotive force signal from the primary actuator. The primary error signal is produced by modifying the primary input signal with the reconstructed error signal.

Abstract: A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if either of the outputs are greater than a reference voltage, a control signal is generated which is used to regulate the gain of the variable gain amplifier. In other embodiments, an analog OR function is used as an input to a conventional two input comparator in place of the three input comparator. In another embodiment, outputs of the variable gain amplifier are passed through switches to a scaling circuit which either voltage divides or amplifies and combines the outputs before application to a comparator. In each case, known asymmetries can be compensated for by independent gain control of each of the outputs of the variable gain differential amplifier.

Abstract: Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer.

Abstract: A method in digital stereo camera for creating anaglyphs of a given subject with a pre-set stereoscopic distance (Sd). The camera has a pre-set distance (D) between and an scene plane and a lens plane defined by pair of first and second lenses aligned along a plane. The camera includes a pre-set distance (p) between the lens plane and an image plane. The pair of lenses is coupled to a pair of imagers. The method comprising the steps of: producing a pair of stereo images each having three color channels; cropping each of the pair of images by an amount (b), where b=Sd*(p/D); and combining one color channel from one of the pair of stereo images with two color channels from a second of the pair of stereo images, so that the resulting image comprises three orthogonal color channels. In another embodiment, a digital stereoscopic camera and a computer readable medium for carrying out the above method is described.

Abstract: Fast and efficient photodiodes with different structures are fabricated using CMOS process technology by adapting transistor structures to form the diode structures. The anode regions of the photodiodes correspond to either PLDD regions of PMOS transistors or P-wells of NMOS transistors to provide two different photodiode structures with different anode region depths and thus different drift region thicknesses. An antireflective film used on the silicon surface of the photodiodes is employed as a silicide-blocking mask at other locations of the device.