Abstract: A method for synthesizing a domino logic circuit design (18) from a source circuit definition (14) using a static logic circuit synthesis tool (12) includes generating a preliminary domino logic circuit (26) design using the circuit synthesis tool (12) and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design (30).

Abstract: A circuit includes a buffer for receiving and storing two samples of a signal, and a phase calculation circuit for calculating from the samples a phase difference between one of the samples and a predetermined point of the signal. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the sector preambles and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery loop uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing an initial coarse alignment, the recovery loop reduces the overall alignment-acquisition time.

Abstract: A smart card includes a card body and integrated circuit carried by the card body, including a microprocessor operative for communicating with a host and driving a signaling device indicative of smart card transactions between the smart card and a USB port of the host. The microprocessor is operative for modulating the signaling device based on operational attributes of the smart card and/or transactions between the smart card and USB port of the host.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers.

Abstract: A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve/lookahead descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and −V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and −V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (−V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage.

Abstract: A cache system and a method for an extent-based cache memory design are disclosed. The method Includes providing a storage device and a host device where each device is in communication with the memory and creating an extent record associated with the memory. A storage device access request is received from the host device and at least one state field value in the extent record is changed in response to the access request from the host device. The size of an extent associated with the extent record and allocated within the memory may be based on the access request and any additional speculative data. The at least one state field value may be selected from the group consisting of extent size, valid count, hit count, and dirty count. The storage device may be implemented as an intelligent hard disk drive and the memory may be implemented by random access memory (RAM).

Abstract: The invention comprises a lid that is capable of being placed in contact with and attached to an integrated circuit that has an exposed surface of an integrated circuit die. The lid has portions that form a cavity between a surface of the lid and the exposed surface of the integrated circuit die when the lid is placed in contact with the integrated circuit. The lid also has portions that form a first fluid conduit for transporting a fluid into the cavity and a second fluid conduit for transporting the fluid out of the cavity. Heat from the integrated circuit die is absorbed by the fluid by direct convection and removed from the integrated circuit when the fluid is removed from the cavity.

Abstract: A system and method simulates a universal serial bus (USB) smart card device connected to a USB host device for development and debugging and includes a computer simulator and USB host device with host controller operatively connected along a communications link with the computer simulator for transmitting or receiving data packets to or from the computer simulator. A microcontroller is located between the computer simulator and USB host device and translates the data packets into a USB protocol to be used by the USB host device and defined by the computer simulator.

Abstract: A method in a digital camera for image capturing at least two perspective images at a constant focal length from the digital camera, where both images share a common edge portion. The method including: recording a first image from a first perspective; displaying a preview of a second image from a second perspective; simultaneously with displaying the preview, presenting an overlapping edge region of the first image to allow alignment of the first image with the preview of the second image; and correcting the perspective of at least one image in an overlapping edge region. In an alternate embodiment, a digital camera and computer readable medium corresponding to the above method is described.

Abstract: There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters, an instruction cache and a power-down controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The power-down controller monitors the instruction cache and each instruction execution pipeline to identify power-down conditions associated with the same and, in response to an identified power-down condition, at least one of: (i) bypasses performance of at least a portion of subsequent ones of the N processing stages associated with an executing instruction, (ii) powers down the instruction cache, and (iii) powers down the data processor.

Abstract: A preformed adhesive layer for joining components within integrated circuit packaging includes venting slots for controlling the size and location of voids within an assembled integrated circuit package. Air randomly entrapped between the surfaces of the adhesive layer and adjoining components during assembly will generally release into the venting slots during subsequent assembly and/or mounting steps performed at elevated temperatures, rather than creating internal pressures causing separation of package components or releasing into the encapsulant. Die delamination and encapsulant void problems occurring during reflow or other assembly and mounting processes as a result of entrapped air are avoided.

Abstract: A microfuel cell includes a substrate and a plurality of spaced-apart PEM dividers extending outwardly to define anodic and cathodic microfluidic channels. An anodic catalyst/electrode lines at least a portion of the anodic microfluidic channels, and a cathodic catalyst/electrode lines at least a portion of the cathodic microfluidic channels. Each anodic and cathodic catalyst/electrode may extend beneath an adjacent portion of a PEM divider in some embodiments. Alternately, the microfuel cell may include a plurality of stacked substrates, in which a first substrate has first microfluidic fuel cell reactant channels. A PEM layer may be adjacent the first surface of the first substrate, an anodic catalyst/electrode layer may be adjacent one side of the PEM layer, and a cathodic catalyst/electrode layer may be adjacent an opposite side of the PEM layer. An adhesive layer may secure the first substrate to an adjacent substrate defining at least a second microfluidic fuel cell reactant channel.

Abstract: An electronic device includes a motion sensitive power switching integrated circuit, which, in turn, includes a power switch connected between an input and an output, and a MEMS inertial sensing switch movable from a first position to a second position based upon motion thereof. The motion sensitive power switching integrated circuit also includes a detector operating the power switch to supply power to the output from the input based upon the MEMS inertial sensing switch moving from the first position to the second position. The first and second positions may be, respectively, a normally open position and a closed position. The device may be unpowered until the MEMS inertial sensing switch moves from the open to the closed position. The detector may generate a power on reset (POR) signal based upon the MEMS inertial sensing switch moving from the open to the closed position.

Abstract: A semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, a layer of undoped silicate glass disposed on the dielectric layer, a layer of borophosphorous silicate glass on the layer of undoped silicate glass, and a planar dielectric layer disposed on the layer of borophosphorous silicate glass, the layers of undoped silicate glass, borophosphorous silicate glass, and planar dielectric together forming a pre-metal dielectric stack. The planar dielectric may include plasma-enhanced tetraethyl orthosilicate.

Abstract: A touch-sensitive semiconductor chip having a physical interface to the environment, where the surface of the physical interface is coated with a fluorocarbon polymer. The polymer is highly scratch resistant and has a characteristic low dielectric constant for providing a low attenuation to electric fields. The polymer can be used instead of conventional passivation layers, thereby allowing a thin, low dielectric constant layer between the object touching the physical interface, and the capacitive sensing circuits underlying the polymer.

Abstract: A power driver for driving a signal on a load using voltage-mode driver. A system processor generates commands indicating a programmed drive signal desired from the voltage-mode driver. A VBEMF compensator determines a compensated command to compensate for the back electromotive force voltage produced by the load. The compensated commands are coupled to the voltage-mode driver, such that the voltage-mode driver generates a voltage output based upon the compensated command.

Abstract: Circuits and methods for generating a reset signal are disclosed. A reset driver circuit receives a reset signal from a circuit, e.g., a reset generator and an input signal indicative of a required characteristic of a reset signal for a second circuit. The reset driver compares a characteristic of the reset signal with the input signal indicative of a required characteristic of a reset signal for a second circuit and generates an output signal that includes the required characteristics of the reset signal for a second circuit. A reset driver circuit may be placed in a communication path between a conventional reset generator and a second circuit that requires a reset signal.

Abstract: A touch-sensitive semiconductor chip having a physical interface to the environment, where the surface of the physical interface is coated with a fluorocarbon polymer. The polymer is highly scratch resistant and has a characteristic low dielectric constant for providing a low attenuation to electric fields. The polymer can be used instead of conventional passivation layers, thereby allowing a thin, low dielectric constant layer between the object touching the physical interface, and the capacitive sensing circuits underlying the polymer.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.