Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract: A method of fabricating an integrated circuit sensor package. The method comprises the steps of: 1) mounting a substrate on a first mold block, the substrate comprising a substantially planar material having a first substrate surface and a second substrate surface that contacts a mounting surface of the first mold block; 2) placing an adhesive on the first substrate surface; 3) placing an integrated circuit sensor on the adhesive; and 4) pressing a second mold block against the first substrate surface. The second mold block comprising a cavity portion for receiving the integrated circuit sensor, a contact surface surrounding the cavity portion, and a compliant layer mounted with the cavity portion. Pressing the second mold block against the first substrate surface causes the contact surface to form with the first substrate surface a seal surrounding the integrated circuit sensor.

Abstract: A VLSI contact formation process in which a nitride layer is used to stop a wet oxide etch. An anisotropic plasma etch is used to cut a substantially vertical contact hole through the nitride and underlying layers. Thus, the resulting contact hole has a “Y”-shaped profile.

Abstract: There is disclosed a memory capable of storing a present value and at least one past value of a variable accessible by a first memory address. The memory comprises a memory block comprising R rows of memory cells and a row address decoder for decoding the first memory address. During a read operation, the row address decoder causes data to be retrieved from a row in which data stored to the first memory address was last written. During a write operation, the row address decoder causes data to be stored in a next-sequential row following the last-written row.

Abstract: An integrated circuit is used in a smart card device and includes at least one memory for storing mass storage data. The smart card device communicates through a chip/smart card interface (CCID) in accordance with the International Standards Organization 7816 (ISO 7816) protocol and a mass storage interface. A microprocessor is connected to the at least one memory and operative for initiating communications with the host using a CCID interface and transferring mass storage data using a mass storage interface.

Abstract: The present invention is a smart card device that can be debugged and software developed using at least one interrupt endpoint without adding an additional port. At least one memory stores a debug monitor program and instructions for completing smart card transactions. An interface is defined by a plurality of communication pipes and respective endpoints, including at least one interrupt endpoint. A microprocessor is operatively connected to the interface and memory and configures the interrupt endpoint as a debug port for debugging and software development using the debug monitor program.

Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.

Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair.

Abstract: The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention obviates the need for phase locked loop (PLL) macrocells to provide timing reference and timing signals in the IC. The ICs of the present invention are preferably used as disk drive integrated circuits that include DSP, memory, data path controllers, data interfaces, custom macrocells, and DSP peripherals. The high-speed serial interface is preferably a Serial ATA (SATA), Universal Serial Bus (USB), Fiber Channel, or Serial Attached SCSI (SAS), among others.

Abstract: A system and method for transmitting and receiving secure e-mails is disclosed. A smart card device stores both private and public keys for an encryption algorithm. The smart card device is preferably a USB smart card device and interfaces a host having a client e-mail program. E-mails are transferred to and/or from the client e-mail program and e-mail server via the smart card while decrypting and encrypting any transmitted and/or received e-mails within the smart card device. The smart card device stores an IP address for an e-mail server. A Simple Mail Transfer Protocol outgoing parameter is set from the client e-mail program to an IP address for the smart card device.

Abstract: There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters and an interrupt and exception controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The interrupt and exception controller operates to (i) detect an exception condition associated with one of the executing instructions, wherein this executing instruction issued at time t0, and (ii) generate an exception in response to the exception condition upon completed execution of earlier ones of the executing instructions, these earlier executing instructions issued at time preceding t0.

Abstract: A method for providing a leadframeless package structure is provided. The method includes providing a temporary carrier. The temporary carrier is coupled to a metal foil layer with a temporary adhesive layer. An integrated circuit chip is coupled to the metal foil layer. The temporary adhesive layer and the temporary carrier are removed to form the leadframeless package structure after molding.

Abstract: A photodetector is integrated on a single semiconductor chip with bipolar transistors including a high speed poly-emitter vertical NPN transistor. The photodetector includes a silicon nitride layer serving as an anti-reflective film. The silicon nitride layer and oxide layers on opposite sides thereof insulate edges of a polysilicon emitter from the underlying transistor regions, minimizing the parasitic capacitance between the NPN transistor's emitter and achieving a high frequency response. The method of manufacture is compatible with existing BiCMOS process technology, the silicon nitride layer of the anti-reflective film being formed over the photodetector as well as regions of the chip that include the vertical NPN transistor and other circuit elements.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers.

Abstract: A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.

Abstract: A system and method is disclosed for venting pressure from an integrated circuit package that is sealed with a lid. During a surface mount process for mounting a ball grid array integrated circuit package to a circuit board the application of heat (1) weakens the solder that seals a soldered lid, and (2) increases vapor pressure within the integrated circuit package. This may cause the soldered lid to move out of its soldered position. The present invention solves this problem by providing an integrated circuit with a solder mask that has a plurality of solder mask vents that form a plurality of vapor pressure vents through the solder. The vapor pressure vents prevent the occurrence of any increase in vapor pressure that would shift the soldered lid out of its soldered position. An alternate embodiment vents pressure through an epoxy layer that is used to attach a lid by epoxy.

Abstract: A compound camera system for generating an enhanced virtual image having a large depth-of-field. The compound camera system comprises a plurality of component cameras for generating image data of an object and a data processor for generating the enhanced virtual image from the image data. The data processor generates the enhanced virtual image by generating a first component virtual image at a first depth plane, generating a second component virtual image at a second depth plane, and inserting first selected pixels from the first component virtual image into enhanced the virtual image and inserting second selected pixels from the second component virtual image into the enhanced virtual image.

Abstract: A compound camera system comprising component cameras that generate image data of an object and a processor that receives first image data from a first component camera and second image data from a second component camera and generates a virtual image. The processor projects virtual pixel data (u,v) to generate point data (x,y,z) located at depth, z=Z1, of a object plane of the object and projects the said point data (x,y,z) to generate first pixel data (u1,v1) located at a image plane of the first image. The processor also projects said point data (x,y,z) located at the depth, z=Z1, of the said object plane to generate second pixel data (u2,v2) located at the second image.

Abstract: A method and apparatus for buffering 2-dimensional graphical image data to be supplied to a scrolling display controller. A 2-dimensional, circularly addressed data buffer is used to store a portion of an entire image. The data buffer is larger than the amount of data displayed at one time. A user enters scrolling commands and the display scrolls around the data initially in the buffer. New data is loaded into the buffer as the displayed data approaches the edge of the buffered data.

Abstract: A signature structure and method of use for verifying a programmed state of a memory circuit of an integrated circuit is disclosed. The integrated circuit comprises a memory cell, a built-in-self-test cell, a compare cell and a signature cell. The signature cell includes a set of first conductive paths in a first level of conductive material and a set of second conductive paths in a second level of conductive material. The first level of conductive material is separated from the second level of conductive material by an insulating material. A contact structure is placed in a manner such that a first conductive path is in electrical contact with a second conductive path. The selection of a placement of the contact structure is such the first and second conductive paths are electrically coupled to a voltage reference source. The combination of the coupled and uncoupled first and second conductive paths provide the bit states of a reference signature word.