Abstract: An inkjet print head includes a semiconductor substrate having a plurality of continuous slotted recesses in a first surface. The plurality of continuous slotted recesses is arranged in parallel, spaced apart relation. Each continuous slotted recess extends continuously across the first surface. The semiconductor substrate also has a plurality of discontinuous slotted recesses in a second surface that is opposite the first surface. The plurality of discontinuous slotted recesses is aligned and coupled in communication with the continuous slotted recesses to have a first portion defining a plurality of alternating through-wafer channels and a second portion defining residual slotted recess portions. A dielectric material is disposed within the residual slotted recess portions. A plurality of inkjet heaters is carried by said semiconductor substrate.

Abstract: A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a test data source and a test data target. A debug chain is coupled between the test data source and test data target, and operates in either a clock debug mode or a test mode. The debug chain, when in the test mode, is deactivated. The debug chain, when in the clock debug mode, receives the test pattern data from the test data source and stores the test pattern data, generates a clock debug signature from the stored test pattern data while clocked by a test clock, and outputs the clock debug signature to the test data target, the clock debug signature indicative of whether the test clock is operating properly.

Abstract: A system in package encloses a sensor and motor driver circuit. In an implementation, the sensor is an integrated circuit micro-electro-mechanical-systems (MEMS) sensor and the driver circuit is a motor driver circuit. Non-motor winding data information is sensed by the MEMS sensor and processed for the purpose of characterizing known fault patterns for motors; characterizing normal operation of the motor; and evaluating continued operation of the motor to detect abnormal motor behavior and instances of motor fault. The motor is driven using PWM control and the information output by the MEMS sensor is sampled at sampling times having a fixed timing relationship relative to the PWM control signals.

Abstract: A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material.

Abstract: A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

Abstract: A method and near field communications (NFC) system for sensing at least one of an environmental condition or a composition of media in a proximity of the NFC system are provided. In the method and system, a first antenna irradiates an electromagnetic field during a sensor mode. A second antenna detects the electromagnetic field and outputs a voltage representative of the detected electromagnetic field. An NFC controller receives a signal representative of the voltage. The NFC controller determines at least one of the environmental condition or the composition of media based on an association stored in memory between the voltage and the at least one of the environmental condition or the composition of media.

Abstract: An embodiment is an integrated System on Chip (SoC) including a communication interface configured to implement a communication protocol including functional blocks that are energized or de-energized individually so that a minimum power consumption is used to receive and detect a signal, and a receiver identification (ID) detection function configured to determine whether the signal is intended for the device in which the SoC resides. The SoC further includes a power management function configured to control which functions in the SoC and/or device in which the SoC resides are energized or de-energized depending on the results of the receiver ID detection function, and a power source capable of energizing a minimum number of the functional blocks required to receive and detect a signal, wherein the power source can be used in a low power state and switched over to a main power supply when the SoC is energized.

Abstract: An electronic device includes a time-of-flight sensor configured to sense a distance between the electronic device and at least one object proximate the electronic device. Processing circuitry is coupled to the time-of-flight sensor and controls access to the electronic device based on the sensed distance. The electronic device may include a digital camera that the processing circuitry controls to perform facial or iris recognition utilizing the sensed distance from the time-of-flight sensor.

Abstract: Disclosed herein is a device including a MEMS sensor configured to generate a first differential capacitance representing a change in capacitance from a first original sensing capacitance value and a second differential capacitance representing a change in capacitance from a second original sensing capacitance value, with the first and second original sensing capacitance values being mismatched. A compensation circuit is configured to generate outputs for compensating the first and second differential capacitances for the mismatch. A capacitance to voltage converter receives the first and second differential capacitances and the outputs of the compensation circuit as input and generates an output voltage as a function thereof.

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

Abstract: The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.

Abstract: The present disclosure is directed to a system that is configured to eject fluid vertically away from a thermal microfluidic die for use with scented oils or other fluids. The die is coupled to a rigid planar support board that separates the die from a reservoir of the fluid. The support board includes an opening that is lined with an inert liner that protects an interior surface of the support board from the fluid. The support board includes contact to an external power supply and contacts to the die on a first surface. The die is coupled to this first surface such that the second surface remains free of electrical connections.

Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.

Abstract: An electronic device includes a printed circuit board (PCB) having at least one conductive trace thereon. A system on chip (SoC) is mounted on the PCB and electrically coupled to the conductive trace. A sensor chip is mounted on the PCB in a spaced apart relation with the SoC and electrically coupled to the conductive trace such that the sensor chip and SoC are electrically coupled. The sensor chip includes an accelerometer and/or a gyroscope, and a control circuit. The control circuit is configured to receive configuration data as input, acquire data from the accelerometer and/or the gyroscope. The control circuit is also configured to process the data so as to generate a context of the electronic device relative to its surroundings, the processing being performed in using a processing technique operating in accordance with the configuration data, and output the context.

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

Abstract: A drive circuit having asymmetrical drivers. In an embodiment, a brushless DC motor may be driven by a drive circuit having three high-side MOSFETs and three low-side MOSFETs. A driver controller turns the MOSFETs on and off according to a drive algorithm such that phase currents are injected into motor coils to be driven. The high-side MOSFETs may be sized differently than the low-side MOSFETs. As such, when a MacDonald waveform (or similar drive algorithm) is used to drive the phases of the motor, less power may be required during disk spin-up because the MOSFETs that are on more (e.g., the low-side MOSFETs with a MacDonald waveform) may be sized larger than the MOSFETs that are on less (e.g., the high-side MOSFETs). In this manner, less power is dissipated in the larger size MOSFETs that are on more than the others.

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.