Abstract: A FinFET includes a semiconductor fin supporting a first transistor and a second transistor. A first transistor gate electrode extends over a first channel region of the fin and a second transistor gate electrode extends over a second channel region of the fin. Epitaxial growth material on a top of the fin forms a raised source region on a first side of the first transistor gate electrode, an intermediate region between a second side of the first transistor gate electrode and a first side of the second transistor gate electrode, and a raised drain region on a second side of the second transistor gate electrode. The first and second transistor gate electrodes are short circuit connected to each other, with the first transistor configured to have a first threshold voltage and the second transistor configured to have a second threshold voltage different from the first threshold voltage.

Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract: A substrate processing apparatus includes an enclosure defining a reaction chamber, a substrate holder in the reaction chamber, and a door assembly. The door assembly has a substrate entrance with a tunnel extending to the reaction chamber, a door movable with respect to the substrate entrance, and a pattern of features. The features are located along a portion of the substrate entrance defining the tunnel. The features promote sticking of processing byproducts, produced in the reaction chamber, to the substrate entrance. A door mates with the entrance to form a seal that reduces flow through the tunnel to control the amount of byproducts that enter the tunnel.

Abstract: A method of making packaged integrated circuit (IC) devices includes mixing a waste thermoset polymer material with a thermosetting polymer to form a mixed thermosetting polymer and packaging IC devices in a molding operation using the mixed thermosetting polymer to thereby recycle the waste thermoset polymer material. A packaged IC device includes an IC device and an encapsulating material surrounding the IC device. The encapsulating material includes a thermoset polymer matrix and thermoset polymer particles dispersed in thermoset polymer matrix.

Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

Abstract: Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal.

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract: On a substrate formed of a first semiconductor material, a first overlying layer formed of a second semiconductor material is deposited. A second overlying layer formed of a third semiconductor material is deposited over the first overlying layer. The first and second overlying layers are patterned to define fins, wherein each fin includes a first region formed of the third material over a second region formed of the second material. An oxide material fills the space between the fins. A thermal oxidation is then performed to convert the second region to a material insulating the first region formed of the third material from the substrate. As an optional step, the second region formed of the second material is horizontally thinned before the oxide material is deposited and the thermal oxidation is performed. Once the fins are formed and insulated from the substrate, conventional FinFET fabrication is performed.

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract: A method and integrated circuit structure. The method includes reducing sidewall height nonuniformity in sidewall image transfer processes by depositing an organic planarization layer over the integrated circuit structure after sidewall definition, mandrel removal, and etch of exposed portions of a first underlying layer in a sidewall image transfer process that is thick enough to cover one or more first sidewalls having a first height and one or more second sidewalls having a second height with the first height greater than the second height, removing a part of the organic planarization layer leaving a first depth of the one or more first sidewalls exposed, removing the exposed first depth of the one or more first sidewalls, and removing the remaining organic planarization layer.

Abstract: A micro device includes a substrate and a structure configured to bind to an object or a material, or not to bind to an object or material. The structure has a roughness based on a roughness of the object or material. For example, a microarray includes a substrate and a well positioned in the substrate and configured to bind to a type of bead. The well has a roughness based on a roughness of the type of bead to which the well is configured to bind. The roughness of the well is controlled by controlling a position and number of striations in the side of the well. In another example, a moveable component of a micro device may have a roughness different from a roughness of an adjacent component, to reduce the likelihood of the moveable component sticking to the adjacent component.

Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made on the bottom portion to produce a silicon-germanium region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract: A device and method for manufacturing integrated circuit packaging using a mold plunger with position compensation in a manufacturing setting. In an embodiment, a compensating mold plunger, which may be used during the manufacture of an integrated circuit package, engages a die set on a carrier and within a bushing. This may be done to inject a mold compound on top of the die/carrier. If the bushing that is housing the die/carrier tandem is misaligned with the plunger in any lateral direction, the amount of pressure may be compromised. A compensating mold plunger includes a flexible portion that allows for the head of the plunger to properly engage the die/carrier despite any possible misalignments. Further, different die/carrier combinations may also be used with a compensating mold plunger because the pressure and force applied may be uniform inside a bushing despite the contents of the bushing.

Abstract: A method of manufacturing double-sided semiconductor die by performing a first plurality of processes to a first side of a wafer and performing a second plurality of processes to a second side of the wafer, thereby forming at least a first semiconductor device on the first side of the wafer and at least a second semiconductor device on the second side of the wafer. The wafer may be cut to form a plurality of die having at least one semiconductor device on each side.