Patents Assigned to STMicroelectronics, Inc.
  • Leadless packages and method of manufacturing same
    Patent number: 9012268
    Abstract: Embodiments of the present disclosure are directed to leadframe strips and methods of forming packages that include first separating adjacent leads of a leadframe strip and subsequently singulating components into individual packages. In one embodiment, the adjacent leads are separated by etching through the leads, thereby providing electrical isolation of the adjacent packages. In that regard, if desired, the individual adjacent packages may be electrically tested in leadframe strip form. Subsequently, the individual packages are formed by sawing through the encapsulation material.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Jonathan Jaurigue, Rogelio Real, Francis Ann Llana, Ricky Calustre, Rodolfo Gacusan
  • Method and system for determining and dispensing resin for a compression molding process flow
    Patent number: 9011127
    Abstract: The present disclosure is directed to a system and method for forming a plurality of packaged dice on a carrier, the carrier including a storage medium configured to store an indication of a total number of unpackaged dice on the carrier. The forming includes providing a quantity of molding compound to a molding module based on the total number of the unpackaged dice on the carrier. The providing includes accessing the indication of the total number of the unpackaged dice on the carrier from the storage medium, determining the quantity of molding compound based on the indication of the total number of unpackaged dice on the carrier, and molding the unpackaged dice into the packaged dice using the quantity of molding compound.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics Inc.
    Inventors: Wiljee Carino, Bernie Chrisanto Ang, Richard Laylo
  • Method and apparatus for reducing power consumption in a wireless communication device
    Patent number: 9014744
    Abstract: A method and apparatus for conserving power in a wireless communication device. The method includes receiving at least a portion of a PHY protocol data unit (PPDU) frame, where the PPDU frame includes an aggregate MAC protocol data unit (A-MPDU) field. The method also includes comparing a receiver address (RA) within the A-MPDU field to a stored address of the wireless communication device and, if the received RA does not match the stored address, causing power to be removed from one or more circuits of the wireless communication device for a calculated period of time.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Liwen Chu, George A. Vlantis
  • NOVEL METHOD TO MAKE HIGH ASPECT RATIO VIAS FOR HIGH PERFORMANCE DEVICES INTERCONNECTION APPLICATION
    Publication number: 20150102496
    Abstract: Metal interconnections are formed in an integrated circuit by forming a wide trench in a dielectric layer. A dielectric fin of a second dielectric material is formed in the trench. Conductive plugs and metal lines are formed on both sides of the fin.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Applicant: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • SEMICONDUCTOR DEVICE INCLUDING STRESS LAYER ADJACENT CHANNEL AND RELATED METHODS
    Publication number: 20150102410
    Abstract: A method for making a semiconductor device may include forming a gate on a semiconductor layer, forming sidewall spacers adjacent the gate, and forming raised source and drain regions defining a channel in the semiconductor layer under the gate. The raised source and drain regions may be spaced apart from the gate by the sidewall spacers. The method may further include removing the sidewall spacers to expose the semiconductor layer between the raised source and drain regions and the gate, and forming a stress layer overlying the gate and the raised source and drain regions. The stress layer may contact the semiconductor layer between the raised source and drain regions and the gate.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 16, 2015
    Applicants: GLOBALFOUNDRIES INC, STMicroelectronics, Inc.
    Inventors: QING LIU, Xiuyu Cai, Ruilong Xie
  • SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE AND RELATED METHODS FOR MAKING SAME USING NON-OXIDIZING THERMAL TREATMENT
    Publication number: 20150102412
    Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 16, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: PIERRE MORIN, Qing Liu, Nicolas Loubet
  • Memory device having multiple dielectric gate stacks and related methods
    Patent number: 9006816
    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: April 14, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris
  • SEMICONDUCTOR DEVICE WITH A BURIED OXIDE STACK FOR DUAL CHANNEL REGIONS AND ASSOCIATED METHODS
    Publication number: 20150097244
    Abstract: A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. A semiconductor layer is formed on the second oxide layer. First and second channel regions are formed in the semiconductor layer.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: QING LIU, Nicolas Loubet
  • METHOD OF MAKING A SEMICONDUCTOR DEVICE USING TRENCH ISOLATION REGIONS TO MAINTAIN CHANNEL STRESS
    Publication number: 20150099335
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: Qing LIU, Nicolas LOUBET
  • SEMICONDUCTOR DEVICE WITH RELAXATION REDUCTION LINER AND ASSOCIATED METHODS
    Publication number: 20150097212
    Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: Pierre MORIN, Qing LIU, Nicolas LOUBET
  • METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER
    Publication number: 20150099334
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: QING LIU, Nicolas Loubet
  • POST-CMP HYBRID WAFER CLEANING TECHNIQUE
    Publication number: 20150096591
    Abstract: A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing-rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • HYBRID PHOTONIC AND ELECTRONIC INTEGRATED CIRCUITS
    Publication number: 20150097289
    Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • Precision polysilicon resistors
    Patent number: 9000564
    Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 7, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GlobalFoundries, Inc., Samsung Electronics Co., Ltd.
    Inventors: Pietro Montanini, Gerald Leake, Jr., Brett H. Engel, Roderick Mason Miller, Ju Youn Kim
  • Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods
    Patent number: 9000555
    Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, Nicolas Loubet, Prasanna Khare
  • Endpoint detector for a semiconductor processing station and associated methods
    Patent number: 9002493
    Abstract: A semiconductor processing apparatus includes a semiconductor processing station for a semiconductor wafer, and an endpoint detector associated with the semiconductor processing station. The endpoint detector includes a non-contact probe configured to probe the semiconductor wafer, an optical transmitter configured to transmit an optical signal to the non-contact probe, and an optical receiver configured to receive a reflected optical signal from the non-contact probe. The controller controls the semiconductor processing station based on the reflected optical signal.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: John H. Zhang, Cindy Goldberg
  • FinFET with multiple concentration percentages
    Patent number: 9000498
    Abstract: An apparatus of a semiconductor is provided wherein the apparatus comprises a substrate, a stack, and a fin. The substrate supports the stack and the substrate comprises a first material. The stack provides for the fin and the stack comprises: a strain induced in the stack via the substrate; the first material and a second material; and a plurality of concentrations of the second material with respect to the first material. The fin provides a source and a drain of a field effect transistor.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics, Inc.
    Inventor: Pierre Morin
  • Method to form finFET/trigate devices on bulk semiconductor wafers
    Patent number: 8999815
    Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: April 7, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Junli Wang
  • Layer formation with reduced channel loss
    Patent number: 9000491
    Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare
  • Method of overlapping interconnect signal lines for reducing capacitive coupling effects
    Patent number: 9001605
    Abstract: Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics, Inc.
    Inventor: David V. Carlson