Abstract: Radio frequency (RF) architectures for spectrum access networks are provided. Embodiments of the invention generally provide a radio frequency (RF) architecture for customer premise equipment (CPE) for use in, for example, IEEE 802.22 wireless regional area networks (WRANs). In some embodiments, the CPE RF architecture includes two receive chains with a directional antenna and an omni-directional antenna, respectively. The CPE RF architecture facilitates opportunistic out-of-band spectrum sensing and WRAN signal receiving that are performed in parallel with data transmission.

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract: A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract: An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.

Abstract: A method for providing a priority-based, low-collision distributed coordination function in a wireless network that includes a plurality of stations is provided. The method includes determining a priority for a first station and selecting a back-off time for the first station based on the priority.

Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed, thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

Abstract: Disclosed herein is a microfluidic pumping device having a piezoelectric member positioned above a displaceable membrane. A voltage is applied across the piezoelectric member causing the piezoelectric member to displace the membrane. Displacement of the membrane increases and decreases pressure in a cavity that is below the membrane. The increases and decreases in pressure actuate cantilevered check valve members to facilitate unidirectional liquid flow through the pumping device.

Abstract: Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Abstract: A ring oscillator in a receiver in a multimedia network is adjusted to compensate for factors that may decrease its accuracy over time using a link training signal from a transmitter device in the network. An incoming signal having a known frequency is received at a receiver or sink device from a transmitter, the signal may be a link training signal used for configuring a link between the two devices. In the receiver, an internally generated clock signal is created, the signal having an internal frequency. The incoming signal and the internally generated clock signal are input into a frequency detector which outputs frequency comparison-based data. The internal frequency is based on the comparison-based data such that it is adjusted to be closer to the known frequency of the incoming signal.

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Abstract: Enhanced low power medium access (LPMA) processes involve the enhanced LPMA STA indicating low power capabilities during association and being allocated an AID. The AID(s) for one or a group of enhanced LPMA STA(s) are included in one TIM sent during a different BEACON interval than the AID(s) for another or another group of enhanced LPMA STA(s). In addition, or alternatively, the AID(s) for enhanced LPMA STA(s) are located at an edge of the AID set within a TIM, a portion of the TIM that may be easily truncated and therefore not sent. The enhanced LPMA STAs and associated access point negotiate unique offset and sleepinterval periods for polling or data uplink by the enhanced LPMA STAs.

Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

Abstract: A device for correlating trend data with respect to a patient's weight ankle displacement can identify conditions indicative of congestive heart failure. A weight scale or similar device coupled with imaging mechanism operable to measure ankle displacement collects a plurality of measurements over a period of time. Over time trend analysis of both the patient's weight and the ankle displacement measurements can be obtained and compared to identify whether over a particular sample period an increase in a patient's ankle displacement is or is not correlated with an increase in the patient's weight. When an increase in ankle displacement is identified as not correlating to a corresponding change in the patient's weight an alert can be issued of conditions indicative of congestive heart failure.