Abstract: An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region.

Abstract: An embodiment of a data write path includes encoder and write circuits. The encoder circuit is configured to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is configured to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium.

Abstract: TDLS support in VHT devices is enabled through the use of added VHT fields in the TDLS frames. A VHT TDLS direct link can be setup through a respective TDLS Setup Request/Response with added field announcing VHT Capabilities of the VHT device and the peer device. Added VHT Operation field in the TDLS Setup Confirm frame adds supports between VHT peer devices for non-VHT BSS and VHT BSS. Two VHT STAs can establish wider TDLS channel than BSS operating channel through TDLS establishment. VHT off channel support is enabled by adding Wide Bandwidth Channel Switch field in the TDLS Channel Switch Request frame and no changes to TDLS Channel Switch Response. A VHT Capabilities field is also added to TDLS Discovery Response frame to inform peer devices of device capabilities.

Abstract: A cleaning apparatus for cleaning a semiconductor wafer includes a rotary brush to be positioned to clean the semiconductor wafer, and an optical sensing device associated with the rotary brush to sense a separation distance between a reference position thereon and the semiconductor wafer. An actuator is coupled to the optical sensing device to position the rotary brush based upon the sensed separation distance.

Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.

Abstract: In accordance with an embodiment, a network device includes a network controller and at least one network interface coupled to the network controller that includes at least one media access control (MAC) device configured to be coupled to at least one physical layer interface (PHY). The network controller may be configured to determine a network path comprising the at least one network interface that has a lowest power consumption of available media types coupled to the at least one PHY.

Abstract: An adaptive uniform polishing system is equipped with feedback control to apply localized adjustments during a polishing operation. The adaptive uniform polishing system disclosed has particular application to the semiconductor industry. Such an adaptive uniform polishing system includes a rotatable head that holds a semiconductor wafer, and a processing unit structured to be placed in contact with an exposed surface of the wafer. The processing unit includes a rotatable macro-pad and a plurality of rotatable micro-pads that can polish different portions of the exposed surface at different rotation speeds and pressures. Thus, uniformity across the exposed surface can be enhanced by applying customized treatments to different areas. Customized treatments can include the use of different pad materials and geometries. Parameters of the adaptive uniform polishing system are programmable, based on in-situ data or data from other operations in a fabrication process, using advanced process control.

Abstract: A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor.

Abstract: A method includes generating an encoded data block, dividing the encoded data block into a plurality of sub-blocks, and transmitting the plurality of sub-blocks over a plurality of physical medium attachments. The encoded data block may be generated using 64B/66B encoding, and the data being encoded could first be decoded using 8B/10B decoding. Another method includes receiving a plurality of sub-blocks over a plurality of physical medium attachments, generating an encoded data block using the plurality of sub-blocks, and recovering data encoded in the encoded data block. The data may be recovered from the encoded data block using 64B/66B decoding, and the recovered data may be subsequently encoded using 8B/10B encoding. Each physical medium attachment may be capable of serializing data for transmission over a physical transmission medium (such as printed circuit board tracks or lanes) and deserializing data received over the physical transmission medium.

Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.

Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.

Abstract: A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of the one or more initial openings in the coating layer and through openings in the hard mask layer. The coating layer is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer has one or more initial openings located therein.

Abstract: A method of forming an integrated circuit structure includes forming a cap layer above a first ILD layer of a first metal level, the first ILD layer includes a recess filled with a first conductive material to form a first interconnect structure. Next, a second ILD layer is formed above the cap layer and a via is formed within the second ILD layer as a second interconnect structure of a second metal level. The via is aligned with the first interconnect structure. Subsequently, a portion of the cap layer is removed to extend the via to expose a top portion of the first conductive material then a passivation cap is selectively formed at a bottom portion of the via in the second ILD layer and the passivation cap contacting the top portion of the first conductive material. The passivation cap includes a metal alloy to form an interface between the bottom portion of the via and the first conductive material.

Abstract: Embodiments of the present disclosure are directed to leadframe packages with wettable sides and methods of manufacturing same. In one embodiment, the leads of the leadframe packages have recesses with a curved profile formed therein. The recesses are plated with a solder wettable layer of conductive material that enables solder to flow along the surface during surface mounting of the package to a board, such as a PCB.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: A device for correlating trend data with respect to a patient's weight and lower extremity displacement can identify conditions indicative of congestive heart failure. An imaging mechanism is operable to measure lower extremity displacement over a period of time. An over-time trend analysis of both the patient's weight and the lower extremity displacement measurements is performed to determine whether over a particular sample period an increase in a patient's lower extremity displacement can be correlated with an increase in the patient's weight. When such a correlation does not exist, an alert can be issued of conditions indicative of congestive heart failure.

Abstract: Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner. Conductors, joined to electrically isolating materials, are exposed to electrical fields in such a manner as to form one or more anodes to corresponding cathodes, thus liberating metal ions. The metal ions are then allowed to migrate in a controlled manner from the anode toward the cathode to form a pre-migrated metal. Finally, an inhibitor is applied on top of the pre-migrated metal to prevent further migration.

Abstract: A system and method for improved upstream data transmission. In an embodiment, a cable modem includes a transceiver configured for transmitting data upstream once permission is granted. In between times when permission to transmit is granted, however, the cable modem is configured to prepare as much data as possible for immediate upstream transmission once that very permission is granted. Thus, prior to permission being granted, the cable modem assembles (pre-processes) the data into transmit frames such that the data frames may be stored in a local memory coupled to the transceiver in a “ready-to-go” format. In this manner, the entire amount of time/bandwidth allocated to the cable modem in response to its request for upstream data transmission may be dedicated to actually transmitting data upstream as opposed to consuming time and bandwidth processing the data into data frames after upstream data transmission has been granted.

Abstract: A filter in a DOCSIS bridge performs IP Filtering of incoming Ethernet packets in hardware. The filter includes a parser circuit which, in hardware, parses each of the incoming Ethernet packets and then utilizes the parsed information in combination with a content-addressable memory (CAM) that stores filtering information, to filter and route the incoming Ethernet packets. Detailed statistical data may also be generated to provide information on the type of filtering being performed by the DOCSIS bridge.

Abstract: A system and method suited for improved overall data transmission having a hardware-based transceiver configured for transmitting upstream data with suppressed data packets. In TCP sessions between devices, a server seeks an “acknowledgement” that the downstream data transmission has been received by a client. Some data packets sent upstream may contain only TCP acknowledgement data and therefore may be combined with other purely TCP acknowledgement data packets in order to reduce the impact of the TCP acknowledgement packets on the overall upstream data throughput. In addition, this results in increased TCP performance in the downstream transmission direction as well because the algorithm enables replacing earlier arriving ACK packets with later arriving ACK packets which allows the device to send all TCP ACK information known to the suppressor at the earliest possible time.