Patents Assigned to STMicroelectronics, Inc.
  • Frequency domain multiband dynamics compressor with automatically adjusting frequency band boundary locations
    Patent number: 8903109
    Abstract: A multiband dynamics compressor implements a frequency-domain solution for addressing unwanted magnitude peaks which may occur at the crossover frequency (boundary) between two adjacent frequency bands. The solution proposes making slight adjustments to the frequency band boundary locations, for example on a frame-by-frame basis, in order to prevent a spectral peak in the input signal from being located midway between two frequency bands. The adjustment to the boundary location pushes the energy of the spectral peak substantially into one frequency band for compression.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: December 2, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Earl C. Vickers
  • System and method of combining damascenes and subtract metal etch for advanced back end of line interconnections
    Patent number: 8900990
    Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: December 2, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Walter Kleemeier, Cindy Goldberg
  • METHOD AND APPARATUS FOR FORMING DIGITAL IMAGES
    Publication number: 20140347709
    Abstract: A method and apparatus for acquiring a corrected digital image of an object includes a digital camera operable to capture a plurality of color component images, an imager body and a support arm. The support arm is coupled to the imager body and adapted to support the digital camera. An image processor is provided to produce corrected color component images and an image combiner is provided to combine the corrected color component images to form the corrected digital image. The camera is moveable to more than one position to enable to formation of three-dimensional images or images with increased depth of focus.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Applicant: STMicroelectronics, Inc.
    Inventor: Francis C. STAFFORD
  • METHOD AND APPARATUS FOR WAVELENGTH SPECIFIC CORRECTION OF DISTORTION IN DIGITAL IMAGES
    Publication number: 20140347502
    Abstract: A method and apparatus for digital image correction in which a plurality of received color component arrays received from a digital camera are each corrected for distortion dependent upon the color associated with the array. Other corrections may also be applied, such as for sensitivity non-uniformity in the sensing array or illumination non-uniformity. The corrected color component arrays for each of the plurality of color components are combined to form a corrected digital image. The method and apparatus may be integrated with digital cameras in a variety of applications including, but not limited to, digital document imaging.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Applicant: STMicroelectronics, Inc.
    Inventor: Francis C. STAFFORD
  • INK JET PRINTHEAD DEVICE WITH COMPRESSIVE STRESSED DIELECTRIC LAYER
    Publication number: 20140340450
    Abstract: An ink jet printhead device includes a substrate and at least one first dielectric layer above the substrate. A resistive layer is above the at least one first dielectric layer. An electrode layer is above the resistive layer and defines first and second electrodes coupled to the resistive layer. At least one second dielectric layer is above the electrode layer and contacts the resistive layer through the at least one opening. The at least one second dielectric layer has a compressive stress magnitude of at least 340 MPa.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 20, 2014
    Applicants: STMICROELECTRONICS, INC., STMICROELECTRONICS ASIA PACIFIC PTE. LTD.
    Inventors: MADANAGOPAL KUNNAVAKKAM, TECK KHIM NEO, KENNETH W. SMILEY
  • Diffusing acoustical crosstalk
    Patent number: 8890290
    Abstract: When two loudspeakers play the same signal, a “phantom center” image is produced between the speakers. However, this image differs from one produced by a real center speaker. In particular, acoustical crosstalk produces a comb-filtering effect, with cancellations that may be in the frequency range needed for the intelligibility of speech. Methods for using phase decorrelation to fill in these gaps and produce a flatter magnitude response are described, reducing coloration and potentially enhancing dialogue clarity. These methods also improve headphone compatibility and reduce the tendency of the phantom image to move toward the nearest speaker.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Earl C. Vickers
  • Structure and method for interconnect spatial frequency doubling using selective ridges
    Patent number: 8889506
    Abstract: An integrated circuit die includes a semiconductor substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. Trenches are formed in the first and second dielectric layers. Metal interconnection tracks are formed on sidewalls of the trench on the exposed portions of the second dielectric layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 18, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Method and apparatus for encoding LBA information into the parity of a LDPC system
    Patent number: 8880976
    Abstract: Systems and methods for encoding and decoding at least one logical block address in a low density parity check (LDPC) are disclosed. These systems and methods can include selecting a LDPC Code matrix and a parity check matrix wherein the LDPC Code matrix and the parity check matrix have an orthogonal relationship. These systems and methods may further include encoding a data element using at least some of the LBA bits in the parity bits in a LDPC codeword creating a parity vector using the at least some of the LBA bits in the LDPC codeword.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Anthony Weathers
  • Current limiting for a motor winding
    Patent number: 8878475
    Abstract: Techniques and apparatus for limiting the current through a motor, such as a motor for rotating a rotatable element of a hard drive. The current can be limited based on a threshold. A first threshold value can be set for a first time period. A second threshold value can be set for a second time period in which the current through the motor rises. The second threshold value is lower than the first threshold value. A spike in the supply current upon accelerating the rotatable element of the motor can thereby be reduced or eliminated.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: November 4, 2014
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.R.L.
    Inventors: Frederic Bonvin, Diego Armaroli
  • Semiconductor device including outwardly extending source and drain silicide contact regions and related methods
    Patent number: 8878300
    Abstract: A method for making a semiconductor device may include forming a plurality of semiconductor fins on a substrate, forming a gate overlying the plurality of semiconductor fins, forming respective unmerged semiconductor regions on the semiconductor fins on opposing sides of the gate, and forming a dielectric layer overlying the unmerged semiconductor regions. The method may further include etching the dielectric layer to define contact recesses having recess bottoms exposing the unmerged semiconductor regions, forming a respective semiconductor layer on each of the exposed unmerged semiconductor regions to extend outwardly from adjacent portions of the recess bottom, and siliciding each of the semiconductor layers to define respective source and drain contacts extending outwardly from adjacent portions of the recess bottom.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: November 4, 2014
    Assignees: STMicroelectronics, Inc., Globalfoundries Inc.
    Inventors: Qing Liu, Ruilong Xie
  • Method for manufacturing a hybrid SOI/bulk semiconductor wafer
    Patent number: 8877600
    Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 4, 2014
    Assignees: STMicroelectronics, Inc., STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Claire Fenouillet-Beranger, Stephane Denorme, Nicolas Loubet, Qing Liu, Emmanuel Richard, Pierre Perreau
  • POWER CONVERTER FOR INTERFACING A FLUORESCENT LIGHTING BALLAST TO A LIGHT EMITTING DIODE LAMP
    Publication number: 20140320007
    Abstract: An AC/DC power converter is coupled between a fluorescent ballast circuit and a set of light emitting diodes (LEDs) forming an LED lamp. The power converter converts an AC output from the ballast circuit to a DC current applied to drive operation of the LEDs. The power converter transforms and rectifies the AC output from the ballast circuit to generate a DC output current. An open load protection circuit is coupled to protect the ballast circuit when the LED lamp is not connected. Current control is provided by a transistor having a source/drain conduction path coupled to shunt the DC output current in response to a control signal having a duty cycle generated as a function of a zero-crossing of the AC output and a sensed value of the DC output current applied to the LED lamp.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 30, 2014
    Applicant: STMicroelectronics, Inc.
    Inventors: Thomas Stamm, Jianwen Shao
  • SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS
    Publication number: 20140312423
    Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 23, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES Inc., STMicroelectronics, Inc.
    Inventors: KANGGUO CHENG, BRUCE B. DORIS, ALI KHAKIFIROOZ, QING LIU, NICOLAS LOUBET, SCOTT LUNING
  • DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET
    Publication number: 20140312461
    Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicants: International Business Machines Corporation, Commissariat A L'Energie Atomique Et Aux Energies Alternatives, STMicroelectronics, Inc.
    Inventors: Kangguo Cheng, Bruce B. Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec, Qing Liu, Maud Vinet
  • Method to form finFET/trigate devices on bulk semiconductor wafers
    Patent number: 8866204
    Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 21, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Junli Wang
  • Recessed gate field effect transistor
    Patent number: 8859350
    Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Yiheng Xu, Carl Radens, Lawrence A. Clevenger
  • Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods
    Patent number: 8860123
    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris
  • System and method for color gamut mapping
    Patent number: 8860745
    Abstract: Methods and systems are described for conducting gamut mapping of color video signals from a first color gamut associated with video source to a second color gamut associated with a receiving display device.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Zisheng Le
  • Method and apparatus for power saving during video blanking periods
    Patent number: 8860888
    Abstract: Methods and systems are described for enabling display system power saving during the operation of display devices. An integrated circuit package includes input interface circuitry configured to receive an audio-video data stream having a video signal and timing information and timing extraction circuitry that can identify blanking patterns for the video signal. The package includes timing control circuitry configured to implement a power saving process during the blanking periods of the video signal. The invention further includes methods that support the operation of power saving processes.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Osamu Kobayashi, Gyo Un Choi
  • LAYER FORMATION WITH REDUCED CHANNEL LOSS
    Publication number: 20140299880
    Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.
    Type: Application
    Filed: June 19, 2014
    Publication date: October 9, 2014
    Applicant: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare