Abstract: A key switch matrix circuit includes key switches arranged in rows and columns, each row having a scan line, each column having a sense line. Each key switch is operable to couple a scan line to a sense line. A scan signal delivery circuit supplies scan signals to the scan lines, the scan signals delivering a scan pulse to each row of the key switch matrix circuit in turn. A key switch detection circuit outputs a first signal if a key switch is operated and a scan pulse detection circuit outputs a second signal if a scan pulse is coupled to a sense line. The scan signal delivery circuit begins supplying scan signals in response to the first signal and stops supplying scan signals in response to the second signal. In one embodiment, a processor reads the sense lines in response to the second signal.

Abstract: For use in a pipeline network search engine of a router, a path compression optimization system and method is disclosed for eliminating single entry trie tables. The system embeds in a parent trie table (1) path compression patterns that comprise common prefix bits of a data packet and (2) skip counts that indicate the length of the path compression patterns. The network search engine utilizes the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses that are necessary to traverse the data structure.

Abstract: Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.

Abstract: A microfabricated structure that includes a first layer of material on a substrate, and a second layer of material over the first layer that forms an encapsulated cavity, and a structural support layer added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

Abstract: A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: A data sorter includes a storage sorter that sorts a data set according to a defined criteria; and a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to a key value. The storage sorter includes a priority queue for sorting the data set. The priority queue has M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism includes a plurality of comparison circuits, each of which is capable of detecting whether one of the intermediate sorted data values is equal to the key value or, if no match exists, extracting a minimal value greater than (or less than according to a defined criteria) the key value.

Abstract: In BLDC motors driven via sensorless techniques, the BEMF signals in the motor coils may be used to detect the position of the motor such that speed of the motor may be accurately controlled. When detecting the BEMF signals, however, small perturbations occur which negatively impact the rotational torque of the motor. As a result, torque ripple may occur at regular intervals which may result in inefficiencies as well as audible noise. In various embodiments as described herein, the sampling of the BEMF signals may be done so at pseudo-random intervals such that the overall spectral energy that presents from the BEMF detections may be reduced at specific frequencies (such as fundamental sampling frequencies and harmonics thereof) and spread out over many more frequencies. Thus, despite the overall spectral energy being the same, the amplitude of any given frequency is lower as the sampling of the BEMF is less periodic.

Abstract: In an embodiment, a multi-carrier signal (e.g., an OFDM signal) is received over a channel. Indicators of interference and the channel response at a carrier frequency of the signal are determined, and compared. If the indicator of interference has a particular relationship to the indicator of the channel response, then a data value transmitted at the carrier frequency is recovered from a data value received at the carrier frequency according to a particular data-recovery algorithm. Because the particular data-recovery algorithm may be faster than a conventional data-recovery algorithm, recovering one or more data values with the particular algorithm may increase the speed at which data is recovered from a multicarrier signal as compared to using a conventional data-recovery algorithm.

Abstract: A built-in self test for receiver operation is provided through a testing method that evaluates characteristics of a received signal eye diagram. The receiver receives a serial data signal and applies compensation to that received serial data signal to generate a compensated serial data signal. The properties of an eye diagram associated with the compensated serial data signal are measured. In this context, certain desired eye diagram properties are characterized by parameters indicative of pass/fail criteria for receiver testing. The measured eye diagram properties are then compared against the parameters. A receiver testing conclusion signal is then output based on results of the comparison.

Abstract: An apparatus for a Universal Serial Bus (USB) and wireless smart card is provided. The apparatus includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. Furthermore, an apparatus for a triple-mode smart card is also provided herein. The apparatus for the triple mode smart card includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. The apparatus for the triple mode smart card operates in one of a wireless mode, a USB mode and an International Standards Organization 7816 mode or other wired mode. Furthermore, the apparatus for any of these smart cards could operate in both the wireless and wired mode(s) without conflict, and without switching power off and on to change configuration.

Abstract: A wireless sensor network including a plurality of Smart Sensors coupled to a wide area network such as the Internet via a Wireless Sensor Coordinator. Each wireless sensor network comprises a plurality of Smart Sensors, each operable to measure one or more physical quantities. Each wireless sensor communicates the measured data to a Wireless Sensor Coordinator which then stores the collected data in memory. The Wireless Sensor Coordinator further includes a web server operable to post a web site on a network that is accessible by a common web browser. Upon receiving a request for sensed data via the web site, the Wireless Sensor Coordinator retrieves the appropriate measured and stored data and converts it into HTML format pages which are then posted on the web site for review by the requestor.

Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract: A trimmable resistor for use in an integrated circuit is trimmed using a heater. The heater is selectively coupled to a voltage source. The application of voltage to the heater causes the heater temperature to increase and produce heat. The heat permeates through a thermal separator to the trimmable resistor. The resistance of the trimmable resistor is permanently increased or decreased when the temperature of the resistor is increased to a value within a particular range of temperatures.

Abstract: A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as for example a high-ohmic poly resistor. The method transfers a pattern defined by a mask onto the screening layer by selectively removing portions of the screening layer in accordance with the pattern. Portions of the auxiliary layer that are not protected by the screening layer are removed using a plasma gas selective to the auxiliary layer material, without removing the area of the auxiliary layer that overlays the portion of the circuit component, thereby protecting the circuit component from the plasma gas via the screening layer and auxiliary layer.

Abstract: A design method for an integrated circuit adds spare cells in a System-on-Chip to allow for Engineering Change Orders (ECOs) to be performed at a later stage in the design. This method can be used to provide a second version of the chip having minimal alterations performed in a short cycle time. The spare cells can be divided into combinational and sequential cells. There is an optimum spread of combinational cells in the design for post placement repairs of the chip with just metal layer changes. The method takes into account the drive strength of the spare cells as the main factor in their placement on the chip.

Abstract: A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.

Abstract: A thick metal layer is formed on a semiconductor integrated circuit in multiple different deposition chambers. A first portion of the metal layer is formed in a first deposition chamber, the first thickness being approximately half the target thickness. The substrate is then removed from the first chamber and transported to a second chamber. The deposition of the same metal layer continues in a second chamber, having the same grain structure and orientation. The second portion of the metal layer is grown to achieve the final thickness. By using two different deposition chambers to form the single metal layer, layers in excess of 25,000 angstroms in thickness can be obtained.

Abstract: An embodiment of a motor controller includes a motor driver and a signal conditioner. The motor driver is operable to generate a motor-coil drive signal having a first component at a first frequency, and the signal conditioner is coupled to the motor driver and is operable to alter the first component. For example, if the first component of the motor-coil drive signal causes the motor to audibly vibrate (e.g., “whine”), then the signal conditioner may alter the amplitude or phase of the first component to reduce the vibration noise to below a threshold level.

Abstract: An embodiment of a motor controller includes first and second supply nodes, a motor-coil node, an isolator, a motor driver, and a motor position signal generator. The isolator is coupled between the first and second supply nodes, and the motor driver is coupled to the second supply node and to the motor-coil node. The motor position signal generator is coupled to the isolator and is operable to generate, in response to the isolator, a motor-position signal that is related to a position of a motor having at least one coil coupled to the motor-coil node. By generating the motor-position signal in response to the isolator, the motor controller or another circuit may determine the at-rest or low-speed position of a motor without using an external coil-current-sense circuit.