Abstract: A non-inverting buck boost DC-DC converter operates with a ripple-hysteretic-current-mode-control including: a first state where control signals close a first high side switch and a second low side switch; a second state where control signals close the first high side switch and a second high side switch; a third state where control signals close a first low side switch and the second high side switch; and a fourth state where control signals close the first low side switch and the second low side switch. Control signal peak voltage and valley voltage are detected. Passing between the first, second, third and fourth states is dependent on peak voltage detection, valley voltage detection, expiration of a variable first time interval following entering the second state, and expiration of a fixed second time interval following entering the third state.

Abstract: A digital multiplicand is received. An initial digital multiplier including logical 0s and 1s is also received. The initial multiplier is processed including at the beginning of each string with at least one logical 1 of the initial multiplier, by applying, or not, in a selective manner, a Booth encoding on said string so as to output a final multiplier. The multiplicand is then multiplied by the final multiplier to produce an output.

Abstract: Disclosed is an energy autonomous system including an energy transducer, a first capacitor, a second capacitor having greater capacitance than the first capacitor, and a microprocessor. The microprocessor includes a first terminal electrically coupled to the energy transducer and the first capacitor; a second terminal electrically coupled to the second capacitor; a switch that is in a conductive state in which the switch electrically couples the first terminal and second terminals together, or a nonconductive state in which the switch does not electrically couple first terminal and second terminals together; a voltage detector that detects a voltage at the first terminal; and a processor coupled to the voltage detector and the switch. The processor controls charging of the second capacitor by controlling the switch to be in the conductive state or the nonconductive state based on the voltage at the first terminal detected by the voltage detector.

Abstract: A device includes an assembly of pixels with a first pixel generating an event-based data element and a second pixel generating a light intensity data element. Each first and second pixel includes a portion of a layer that forms a photodiode. A first integrated circuit chip includes a first substrate and a first interconnection network, and a second integrated circuit chip includes a second substrate and a second interconnection network. The first and second integrated circuit chips are attached to each other by the first and second interconnection networks. The layer with the photodiodes is located on a first surface of the second substrate opposite to a second surface of the second substrate having the second interconnection network located thereon.

Abstract: An optical device includes a metasurface formed by a metasurface substrate having at least a first metasurface layer made of a first material and an array of pillars extending through the first metasurface layer. The pillars are made of a second material different from the first material. The metasurface has a first face and a second face opposite the first face. A first anti-reflection stack is positioned over the first face of the metasurface. The first anti-reflection stack has a third face and a fourth face opposite the third face and positioned over the first face of the metasurface. A metal trace has a portion which is exposed at the third face of the first anti-reflection stack.

Abstract: A memory system includes a memory array with first dummy read cells that discharge a dummy bit line, each of the first dummy read cells including a transistor coupled between the dummy bit line and a first ground node that is connected to a ground reference. Second dummy read cells discharge the dummy bit line, each of the dummy read cells including a transistor coupled between the dummy bit line and a second ground node. The dummy read cells cooperate to discharge the dummy bit line in a dummy read operation to provide a self-timing signal. Read circuitry retrieves data from a selected row in the memory array during a read operation, in response to the self-timing signal. Ground generation circuitry connects the second ground node to the ground reference or allows the second ground to float, based upon a control signal.

Abstract: An integrated circuit package includes a support substrate with front connection pads on a front surface thereof and rear connection pads on a rear surface thereof. An integrated circuit device is mounted to the support substrate in flip chip orientation with a front face of the integrated circuit device facing the front surface of the support substrate. A thermally conductive heat spreader is mounted adjacent a rear face of the integrated circuit device. External direct thermal paths thermally couple a top surface of the thermally conductive heat spreader to the rear surface of the support substrate. Each external direct thermal path includes a first portion on and in direct contact with thermally conductive heat spreader, a second portion on and in direct contact with an external side surface of the support substrate and a third portion on and in direct contact with the rear surface of the support substrate.

Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.

Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N?1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N?1 number of redundant flip-flops is observed through the functional path to determine faults.

Abstract: An integrated system for electric-current monitoring includes a package and a MEMS sensor device arranged inside the package to provide an output electrical signal indicative of the electric current to be monitored. A sensing coil is provided within the package. The electric current to be monitored flows through the sensing coil. The MEMS sensor device is arranged relative to the sensing coil so as to be affected by flux lines of a magnetic field generated as a whole by the sensing coil as a function of the electric current to be monitored.

Abstract: A MEMS metamaterial has a substrate and a suspended structure having an elementary cell which extends at a distance from the substrate along a first direction. The elementary cell has a first structural region having a first material with a first coefficient of thermal expansion. The first structural region has a first side facing the substrate and a second side opposite to the first side. The elementary cell also has a second structural region having a second material different from the first material and with a second coefficient of thermal expansion different from the first coefficient of thermal expansion. The second structural region extends on at least part of the first structural region, on the first side, the second side, or both the first and second side of the first structural region.

Abstract: A sensor module includes an organic substrate, a MEMS pressure sensor mounted to the organic substrate, and a unitary lid mounted on the substrate. The unitary lid includes a central elevated portion housing the MEMS pressure sensor, an aperture in the central elevated portion, and a flat flange extending from the central elevated portion to an edge of the organic substrate.

Abstract: A bandgap voltage generator circuit is formed using only bipolar transistors. The bandgap voltage generator circuit includes an output node at which a bandgap reference voltage is generated. A transconductance amplifier circuit in a current control feedback loop has a differential input which receives a base current. A compensation current sink circuit operates to sink a compensation current from the output node corresponding to the base current received at the differential input of the transconductance amplifier.

Abstract: A device includes a sensor and processing circuitry. The sensor, in operation, generates a sequence of data samples. The processing circuitry, in operation, implements a sliding convolutional neural network (SCNN) having a plurality of layers to generate classification results based on the sequence of data samples. The SCNN sequentially processes the sequence of data samples, the sequentially processing the sequence of data samples including, for each received sample of a set of received data samples of the sequence of data samples, iteratively updating partial results of an inference of a first layer of the plurality of layers based on a respective patch of data samples of the sequence of data samples. The respective patch of data samples includes the received data sample. The classification results may be used to generate control signals, such as by the sensing device or a host processor coupled to the sensing device.

Abstract: Disclosed herein a method for transforming a single processor system into an effective multicore system with few modifications to the existing processor. The transformation is achieved by wrapping the processor with a CPU Manager module, which intercepts all CPU transactions, remaps addresses, manages interrupt lines, and controls the CPU clock using clock gating. The transformation to n effective multicore system brings about reduced area and power impacts compared to a full duplication of the whole system, while still reusing the existing program in a multicore environment.

Abstract: A bandgap voltage generator circuit is formed using only bipolar transistors. The bandgap voltage generator circuit includes output nodes generating first and second bandgap reference currents. A transconductance amplifier circuit in a current control feedback loop of the bandgap voltage generator circuit has differential inputs which receive base currents. A differential amplifier circuit has inputs configured to receive the first and second bandgap reference currents and includes a compensation current sink circuit configured to sink compensation currents from the first and second bandgap reference currents which correspond to the base current received at the differential inputs of the transconductance amplifier circuit.

Abstract: The present description relates to an electronic circuit comprising a semiconductor substrate having opposed first and second faces and electrically conductive pillars, intended to be connected to an element external to the electronic circuit, extending through the semiconductor substrate from the second face to the first face and projecting from the first face.

Abstract: A circuit detects zero crosses in an input-signal and includes a low-pass-filter (LPF) receiving the input-signal and introducing a phase-shift dependent on the frequency thereof. Filter circuitry receives the output of the LPF, applies a fixed phase-shift thereto, and adjusts phase and DC-offset thereof based on control signals to produce a filtered output-signal. Control circuitry has a zero-crossing detector receiving the input-signal and the filtered output-signal, detecting zero-crossings of the input-signal and the filtered output-signal, asserting a digital zero cross signal at each zero crossing, and determining a phase-shift and DC-offset between the input-signal and filtered output-signal.

Abstract: Method of forming a metal-semiconductor contact, comprising the steps of: forming, on a semiconductor body having a first electrical conductivity, a first metal layer; performing a thermal treatment of at least a portion of the first metal layer by a LASER beam having an incidence direction on the first metal layer, including heating the portion of the first metal layer, along said incidence direction, at a temperature between 1500° C. and 3000° C.