Abstract: A field programmable device including a plurality of logic blocks; a plurality of configurable connections; at least one switching circuit; and a plurality of lines extending at least partially through the device. In a configuration mode, the switching circuit causes configuration signals to be passed to the configurable connections via the plurality of lines and in a processing mode, the plurality of lines are used in at least one of at least one logic block and at least one connection to carry data.

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract: A method of acquiring a received broadcast signal that includes mixing the signal with a local frequency and digitizing the same to produce a received digitized signal, correlating the received digitized signal with a local version of a repeated code in the signal using a clock derived coherently from a master clock source and again for a second time period that is separated by a separation period for producing first and second results, and combining the first and second correlation results by comparing the location of correlation peaks to reject peaks not appearing at the same position in both the first and second correlation results.

Abstract: A bridge circuit includes two FIFO circuits each having an associated FIFO control circuit. In each FIFO control circuit, a write pointer register and a read pointer register for controlling the storage location for writing to and reading from the FIFO circuit are each controlled by control logic. The control logic is responsive to comparators which receive and compare the write pointer value and the retimed read pointer value to control the write pointer register, and receive and compare the read pointer value and the retimed write pointer value to control the read pointer register. The retiming circuits are configurable in response to a mode signal to provide different degrees of retiming. The maximum number of storage locations that can be full at any one time is a fixed limit.

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

Abstract: A method for changing the bit-order of a data value in a data processing system having a register capable of storing data strings which each comprise a plurality of sub-strings that are not individually addressable, the method comprising assigning an output data string by the steps of: loading the data value into a first data string; generating, for each sub-string of the output data string, a corresponding intermediate data string, each sub-string of which corresponds to a selected bit on the first data string and has all its bits equal to the value of the selected bit; and generating the output data string, in each sub-string of which each bit has the same value as the bits in a selected sub-string of the intermediate data string that corresponds to that sub-string of the output data string.

Abstract: A semiconductor integrated circuit for use in direct memory access (DMA) has two sources which communicate with a bus through a bus interface. A DMA access signal generator is coupled to the bus interface and asserts a DMA access output signal at a DMA access signal pin whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the two sources is thereby avoided. With targets on two separate integrated circuits, a single DMA access pin can be used for the two targets, while chip select signals at chip select pins on the source integrated circuit indicate which of the two targets is intended for the DMA access.

Abstract: The present invention is concerned with a method and apparatus for hardening logic devices. The logic device has a plurality of memory cells forming an array connected by data lines and clock lines, and the device having a further connecting line. The method comprising: receiving data on said data lines for configuring each of the memory cells. Storing data in each of the memory cells by enabling at least one of the clock lines and when the desired data has been stored, hardening the array to fix the data by selectively connecting the data and clock lines to the further line.

Abstract: A voltage reference circuit comprising a first reference voltage source, a second reference voltage source, at least one of said first and second reference voltage sources being dependent on temperature, and first circuitry connected to at least one of said first and second reference voltage sources to provide a third reference voltage, said third reference voltage being dependent on temperature.

Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

Abstract: A controller for controlling direct memory access. Such a controller is particularly applicable when applied to a transport interface in the receiver of a digital set-top-box for television systems. A storage means stores the base and top addresses of a circular buffer in a memory to which received data is to be forwarded and stored, and a write pointer for such buffer is also stored in the storage means. Addressing circuitry generates the address to which the receive data is to be written in dependence on the stored base and top addresses and the write pointer. Output circuitry writes the data into the circular buffer at the location identified by the generated address.

Abstract: An executable program is prepared from a plurality of object code modules, each object code module including section data and associated relocations and at least one of the object code modules further including code sequences at least some of which are like to be repeatedly included in the executable program. Wherever a code sequence is to be inserted, a relocation instruction specifies the location of the code sequence and the code sequence is inserted into the section data at the appropriate point. A linker, a method for assembling, and a computer program product support these operations.

Abstract: An image sensor device includes an image sensor chip and an image sensor array formed on a top surface of the image sensor chip. The image sensor chip is mounted on a substrate and encapsulated by a dam wall formed on the substrate surrounding the periphery of the image sensor chip and a transparent lid member affixed to the upper edges of the dam wall. A barrier is formed on the surface of the chip extending along at least a substantial part of at least one side of the sensor array between the sensor array and the dam wall. The barrier is preferably formed with a height of at least three microns and surrounds the sensor array. The barrier may be formed during fabrication of the sensor chip. Where the sensor chip is a color image sensor including a mosaic of color filter material overlying the image sensor array, the barrier may be formed from the color filter material with the formation of the mosaic. The barrier prevents resin bleeding from the dam wall onto the surface of the sensor array.

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor. An additional instruction monitor checks the code instructions from the CPU and also impairs the operation of the circuit unless the address of code requested is in a given range. The code is in the form of a linked list and the range is derived as a linked list table during a first check.

Abstract: A method is described for distinguishing between an input or output signal on a bi-directional pin of a model of a hardware circuit. The method includes the steps of for a bi-directional pin of said model applying signals to said pin at a reduced drive strength such that a driven signal on said pin will be superimposed over the applied signal, and comparing the drive strength on the bi-directional pin and responsive to said comparison determining whether the bi-directional pin is an input or output.

Abstract: A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load control unit is used to define a plurality of memory regions and has means for checking whether the physical addresses lie within at least one of said defined memory regions. In this way, the control unit allows the mapping of large physical page size to RAM devices and the extra address space is filtered off by the control unit so that speculative loads are not carried out in unknown regions.

Abstract: Solid state image sensors, and methods of operation thereof, includes an array of photosensitive pixels arranged in rows and columns and in which pixel data signals are read out from the pixels via column circuits, which introduces column fixed pattern noise to the signals. The signals are selectively inverted at the inputs to the column circuits and the inversion is reversed following output from the column circuits. Each column circuit may include an analog-to-digital converter and a digital inverter for inverting digital output therefrom. The selective inversion may be applied to alternate rows or groups of rows of the pixel data, and may be applied differently to different frames of the pixel data. These techniques result in column fixed pattern noise being modulated in a manner which makes the noise less apparent to the eye, and which facilitates subsequent cancellation of the noise.

Abstract: A ramp generator includes a resistance ladder (10) supplied with a constant current. Switches are closed in sequence on the resistance ladder to generate the ramp voltage. By using control logic to decode the sequence, a looped shift register is used to close the switches.

Abstract: A video signal is produced from a color imaging array of the type having luminance elements of a first color (typically green) and chrominance elements of second and third colors (typically red and blue). The video signal processing includes, for each element of the second color, estimating a chrominance value of the third color as a function of the actual chrominance value of that element, the local neighborhood of actual chrominance values of the third color, and an anti-aliasing control value derived from the local neighborhood of actual luminance values and actual third color chrominance values. In preferred forms, a similar estimation of the second color at each third color element is performed.

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.