Patents Assigned to STMicroelectronics Limited
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Patent number: 7031903Abstract: A communication device for a target integrated circuit chip having a digital processor, an on-chip emulator for controlling the digital processor and for collecting operation data from the digital processor for communicating to off-chip circuitry, and a target on-chip universal serial bus interface connected to the on-chip emulator, the communication device including an Ethernet port, an universal serial bus port and a further integrated circuit chip having on-chip universal serial bus interface, the on-chip Ethernet interface being connected to the Ethernet port, the interfaces being connected to the processing circuitry for translating between Ethernet protocol data on an Ethernet bus connected to the Ethernet port and universal serial bus data for the target on-chip universal serial bus interface.Type: GrantFiled: October 16, 2001Date of Patent: April 18, 2006Assignee: STMicroelectronics LimitedInventor: Anthony Debling
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Patent number: 7017131Abstract: A method of replacing standard cells with high speed cells in the design of a circuit using a computer program, said application specific integrated circuit design comprising a plurality of high speed cells and a plurality of standard cells, said high speed cells and standard cells being arranged to form a plurality of paths on said application specific integrated circuit, said method comprising the steps of: timing said plurality of paths identifying cells occurring on paths for which timing targets are not met; upgrading at least one of said identified cells to a high speed cell.Type: GrantFiled: July 7, 2003Date of Patent: March 21, 2006Assignee: STMicroelectronics LimitedInventor: Paul Barnes
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Patent number: 7010732Abstract: Test circuitry for testing an integrated circuit, the integrated circuit being configurable to accept input data from stimulus scan cells and to provide output data to response scan cells, the test circuitry including stimulus circuitry for providing test data to the integrated circuit; input selection means operable to control which of the test data and the input data are received at the integrated circuit; capture circuitry for capturing output data from the integrated circuit and generating response data; output selection means operable to select which of the output data and the response data are received by the response scan cells.Type: GrantFiled: February 6, 2002Date of Patent: March 7, 2006Assignee: STMicroelectronics LimitedInventors: Steven Firth, William Bryan Barnes
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Patent number: 7007272Abstract: This patent describes a method of compiling a computer program from a sequence of computer instructions including a plurality of first, set branch, instructions which each identify a target address for a branch and a plurality of associated second, effect branch instructions which each implement a branch to a target address. The method comprising the steps of: reading the computer instructions in blocks; allocating each set branch instruction to an initial node in a dominator tree, the initial node being the node which contains the corresponding effect branch instruction; for the first determining the effect of migrating set branch instructions to each of a set of ancestor nodes in the dominator tree based on a performance cost parameter and selecting an ancestor node with the best performance cost parameter; locating said set branch instruction at the selected ancestor node.Type: GrantFiled: October 10, 2001Date of Patent: February 28, 2006Assignee: STMicroelectronics LimitedInventor: Stephen Clarke
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Publication number: 20060036888Abstract: An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.Type: ApplicationFiled: July 5, 2005Publication date: February 16, 2006Applicant: STMicroelectronics LimitedInventors: Robert Warren, David Smith
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Publication number: 20060036881Abstract: Disclosed in this patent document is a processor circuitry, and a method of operating such processor circuitry, comprising execution circuitry, at least one interrupt controller and an idle monitor, said monitor arranged to determine when said pipeline is idle by detecting an opcode and to determine if said execution circuitry is able to enter the idle state and if so to generate a signal to cause at least the execution circuitry to enter said idle state.Type: ApplicationFiled: May 27, 2005Publication date: February 16, 2006Applicant: STMICROELECTRONICS LIMITEDInventor: Mark Homewood
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Patent number: 6996513Abstract: A method and system for identifying an inaccurate model of a hardware circuit includes the steps of simulating a digital model and an analogue model of the circuit to provide first and second sets of simulation results respectively. For each result in the first and second sets of simulation an integer value is determined which represents that result. The integer values are stored in first and second sets of comparison results respectively and the sets of comparison results are compared. An output signal indicating that at least one of the models is inaccurate is produced if the comparison results contradict.Type: GrantFiled: June 7, 2001Date of Patent: February 7, 2006Assignee: STMicroelectronics LimitedInventor: Peter Bellam
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Patent number: 6990100Abstract: A method of converting a packet of data from a source format to a target format, the packet including a type indicator and at least one data field, the method including the steps of storing a table for each packet type, each table including for each data field of that packet type a value representative of a storage requirement in memory and a corresponding field descriptor denoting the nature of the data field; receiving a packet in a source format; identifying the type of packet from the type indicator; accessing the stored table for the type of packet identified and thus obtaining for each data field a value representative of a storage requirement in memory and a field descriptor for that field; and using the value and the field descriptor to load the packet into a target memory according to the target format specified by the field descriptor.Type: GrantFiled: March 15, 2001Date of Patent: January 24, 2006Assignee: STMicroelectronics LimitedInventor: Douglas John Turner
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Publication number: 20060010304Abstract: A method of loading an unaligned word from a specified unaligned word address in a memory, said unaligned word comprising a plurality of indexed portions crossing a word boundary, the method comprising: loading a first aligned word commencing at an aligned word address rounded from said specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second aligned words using the identified index to construct the unaligned word.Type: ApplicationFiled: August 19, 2004Publication date: January 12, 2006Applicants: STMICROELECTRONICS LIMITED, HEWLETT-PACKARD COMPANYInventors: Mark Homewood, Paolo Faraboschi
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Patent number: 6982573Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.Type: GrantFiled: April 19, 2004Date of Patent: January 3, 2006Assignee: STMicroelectronics LimitedInventors: Matt Hutson, Andrew Dellow, Tom Ryan, Paul Elliott
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Publication number: 20050284938Abstract: A card reader reads data stored on a card. A contact signal is produced whose state is indicative of the presence or absence of electrical contact between the card and the card reader. A high state indicates the presence of electrical contact and a low state indicates the absence of electrical contact. Upon insertion of the card into the card reader, vibrations and other mechanical perturbations of the card cause the state of the contact signal to fluctuate rapidly between high and low states. The state of the contact signal is periodically sampled for a predetermined period of time and the number of samples for which the contact signal was high are counted. If the number of high samples exceeds a threshold then stable electrical contact is deemed to have been established between the card and the card reader and a system reset is performed.Type: ApplicationFiled: June 14, 2005Publication date: December 29, 2005Applicant: STMicroelectronics LimitedInventors: Jeremy Whaley, Matthew Hutson
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Publication number: 20050285946Abstract: An orientation sensor for use with an image sensor is provided, which includes at least two polarizers with different orientations and associated photodetectors and a signal processing unit. The orientation sensor can be incorporated in a digital camera. When the camera is exposed to daylight, which is polarized, the relative outputs from the differently oriented polarizers can be compared to record the orientation of the camera. This orientation can be stored with the image data so that a user does not have to manually change the orientation of an image on an image display device.Type: ApplicationFiled: June 16, 2005Publication date: December 29, 2005Applicant: STMicroelectronics LimitedInventor: Jeffrey Raynor
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Publication number: 20050285960Abstract: The readout circuit, for an image sensing pixel array, is arranged to perform correlated double sampling and includes readout circuitry which is capable of learning its own internal offset and the offset of both its inputs. In the process of correlated double sampling, one of two sampling capacitors can be made smaller, as the thermal noise it creates is learned. The reduction of size of the appropriate sampling capacitor enables the size of a column multiplexer to be reduced without affecting its noise contribution.Type: ApplicationFiled: June 23, 2005Publication date: December 29, 2005Applicant: STMicroelectronics LimitedInventors: Matthew Purcell, Robert Henderson, J.E.D. Hurwitz
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Publication number: 20050280455Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.Type: ApplicationFiled: May 24, 2005Publication date: December 22, 2005Applicant: STMICROELECTRONICS LIMITEDInventor: Matthew Hutson
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Publication number: 20050278510Abstract: A system comprising execution circuitry for executing instructions and a register file comprising at least one port, the circuitry operating to allow said execution circuitry to share a common port of said register file.Type: ApplicationFiled: May 12, 2005Publication date: December 15, 2005Applicant: STMICROELECTRONICS LIMITEDInventors: Kristen Jacobs, Peter Hedinger
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Publication number: 20050276264Abstract: A system including input circuitry for receiving from one of a plurality of sources at least one packet stream including a plurality of packets for providing audio, video, private data and/or associated information; at least one output for outputting at least one packet of the at least one packet stream to circuitry arranged to provide an output stream; wherein the system is arranged to provide a tag indicative of the source, the tag being associated with the at least one packet.Type: ApplicationFiled: June 3, 2005Publication date: December 15, 2005Applicant: STMicroelectronics LimitedInventors: Rodrigo Cordero, Paul Cox, Andrew Dellow
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Publication number: 20050275473Abstract: A phase locked loop (PLL) circuit comprising: feedback division circuitry for receiving an output signal, the feedback division circuitry arranged to divide the output signal by a first division factor in a first mode of operation, and a second division factor in a second mode of operation.Type: ApplicationFiled: December 17, 2004Publication date: December 15, 2005Applicant: STMICROELECTRONICS LIMITEDInventors: William Thies, Chris Lawley
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Publication number: 20050273540Abstract: The invention provides an interrupt handling system to process a generated interrupt. At least one input is arranged to provide a predetermined active level, with a detection circuit associated with the input which is selectively configurable to detect either the active level or an inactive level. An interrupt request message causes the detection circuit to be configured to detect the active level, so that an enable logic is caused to generate an interrupt. The invention provides an integrated circuit and a method of generating interrupts using the above system, and a consumer electronic device in the form of a set top box or DVD Read and/or Write device.Type: ApplicationFiled: May 11, 2005Publication date: December 8, 2005Applicant: STMICROELECTRONICS LIMITEDInventor: Jeremy Whaley
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Publication number: 20050269609Abstract: A pinned-photodiode image sensor using shared output amplifiers, for example output amplifiers in the 2.5T arrangement has transfer gate control lines alternating or cross-coupled between successive columns or adjacent rows. This assists in removing row-row mismatches. In preferred embodiments, the approach is applied to Bayer pattern RGB sensors, and allows the gain and/or the exposure of green pixels to be controlled separately from those of red and blue pixels.Type: ApplicationFiled: June 3, 2005Publication date: December 8, 2005Applicant: STMicroelectronics LimitedInventor: Robert Henderson
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Publication number: 20050269607Abstract: The image sensor includes an array of pixels. Each pixel has a pinned photodiode which transfers charge via a transfer gate to a floating diffusion, from which output is provided by a source follower. Each column has a voltage supply line and a signal line. Each row has a transfer gate control line, a read/reset control line, and a read/reset voltage line which receives alternately zero volts and a predetermined positive voltage from a decoder circuit.Type: ApplicationFiled: June 3, 2005Publication date: December 8, 2005Applicant: STMicroelectronics LimitedInventor: Robert Henderson
