Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions being allocated to different time slots.

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

Abstract: An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer having a least one control input whereby the multiplexer is controllable to direct test signals to one of the plurality of portions.

Abstract: A method is described for reducing delays in an analogue simulation model of a hardware circuit. The method includes the steps of stimulating via an input an output of said analog model, said output and said input having a relatively high resistance therebetween and applying a pulse to a relatively low resistance, whereby when said pulse is applied to the relatively low resistance, the input is connected to said output via the relatively low resistance so that the time constant of the circuit is reduced.

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals comprises an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. Entitlement messages are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure. Alternatively, the entitlement messages are encrypted for decryption with the common keys and a unique ID stored in the circuit is compared with an ID in a received entitlement message. Only if the received and stored IDs match can the rights be stored and used.

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract: A computer system for simulating an ASP comprises first processor means including execution means for simulating a functional model in a high level language and output means for outputting the state of the functional model at the end of a predetermined simulation phase, means for converting the functional model, including its state at the end of the predetermined simulation phase, into a simulation language for simulating the ASP at circuit level, and second processor means arranged to execute the simulation language to simulate the ASP at circuit level for a subsequent simulation phase.

Abstract: A method for generating a series of digitized control values for an output device to represent a continuous series of source data, comprising the steps of: storing in a single register a first digitized control value and an indication of deviation between that value and the source data; and repeatedly adding an increment to the register to generate a further digitized control value and simultaneously update the indication of deviation.

Abstract: A method of assembling a source code module to form an object code module, said source code module including one or more assembler directives, wherein the assembler directives are used to generate relocation instructions in the object code module, the method comprising: reading a plurality of compound relocation sequence definitions stored in a memory, each compound relocation definition sequence comprising a compound relocation indicator and a first sequence of relocation instructions; reading assembler source code from said source code module, said source code generating an associated sequence of relocation instructions for executing the directive; determining if said associated sequence of relocations matches one of said stored sequence of relocation instructions; and if a match of relocation sequences is determined, inserting into said object code module a compound relocation including the compound relocation indicator of said matched compound relocation sequence definition instruction and said matched se

Abstract: Lighting flicker in the output of a video imaging device is detected. The video imaging device has a main picture area divided into pixels for producing successive images at a frame rate. A series of signals are produced from at least one additional picture area adjacent the main picture area, with the additional picture area having a size substantially larger than a pixel. Each of the signals is a function of light incident on the additional picture area in a time period substantially shorter than that of the frame rate. A predetermined number of the signals are accumulated to form a series of compound samples, and the compound samples are filtered to detect components indicating the lighting flicker. The filtering is performed using a bandpass filter tuned to the nominal flicker frequency. The compound samples are formed at a sample rate which is a multiple of the nominal flicker frequency, and the filtering is performed by taking the fundamental output component of a radix-N butterfly.

Abstract: An oscillator circuit is described comprising of a capacitor; a capacitor charging means arranged to supply a current to charge the capacitor to a first predetermined threshold voltage; a capacitor discharging means arranged to discharge the capacitor to a second predetermined threshold voltage; and a switching means arranged to switch between a capacitor discharging mode and a capacitor charging mode. The switching means is responsive to the capacitor reaching at least one of said threshold voltages. Furthermore at least one threshold voltage is determined by a threshold setting means, which provides a voltage threshold that varies to compensate for changes in temperature.

Abstract: A method of disassembling object code to generate the original source code is discussed, together with a lister for performing the disassembly. The object code has relocation sections associated with some of the section data. For each location in the section data the lister determines if there is an associated relocation instruction and if there is, the lister derives certain additional information concerning the section data. The lister then generates the original source code, including the additional information. One example of the additional information is an arithmetic expression used to calculate a value in a relocation instruction. The set of relocations associated with the location of the instruction are read in turn by the lister and by using an expression calculator and an expression stack, the original arithmetic expression can be reconstructed.

Abstract: A computer system comprising a plurality of data processing elements connected through a shared communication bus to a memory so that for a given computer cycle at least one of the elements assumes control of the bus for accessing address in memory. The computer system having memory access circuitry connected between the data processing elements and memory which has first and second buffer units for storing prefetched bursts of data from the memory. The buffer circuit also having control logic for prefetching data in sequential bursts from the memory and storing the prefetched burst in the first or second buffer units and the control logic monitors the buffer units and the address to be accessed in memory to determine in which buffer the next fetched burst should be stored.

Abstract: A memory map evaluation tool is provided that organizes a program in a manner most compatible with use of a cache. The tool includes a method that involves executing a first version of the program according to a first memory map to generate a program counter trace, converting the program counter trace into a specific format and then translating the program counter trace into physical addresses using a memory map to be evaluated, different from the first memory map. Those physical addresses are then used to evaluate the number of likely cache misses using a model of a direct-mapped cache for the memory map under evaluation.

Abstract: A circuit is used in the output stage of an operational amplifier which allows a rail to rail swing of the output voltage while consuming low quiescent power. The circuit includes first and second control elements each having a controllable path and a control node. The circuit further includes a third control element having a controllable path connected between the control nodes of the first and second control elements via a resistive path. A voltage indicative of an input signal is applied to a node of the resistive path. Current flow through the controllable paths of the first and second control elements changes in response to changes in the voltage at the node. More specifically, current flow through the controllable path of the second control element changes in dependance on the current flow through the controllable path of the third control element. Additionally, as one of the first and second control elements is turned on, the other control element is held off.

Abstract: A method and apparatus are provided for controlling services provided at a first electronic device at a second electronic device. A plurality of electronic devices connected to a network provide services in the form of providing data to the network, or allowing the data to be manipulated. Each service is represented as a manipulable data object created at the device providing the service. Each object contains sufficient information to allow the service the object represents to be controlled. The objects are transmitted over the network and are stored in an object list maintained by a master device. Any compatible device may then retrieve an object from the object list and use the information contained in it to fully control the service.

Abstract: A semiconductor integrated circuit, including a test scan arrangement has a plurality of scan chains arranged in pairs. These scan chains have input terminals for receiving test patterns, and outputs provided to compression logic such as a distributed XOR tree multiple input shift register to provide an output which is a compressed signal derived from the output test patterns. In an alternative configuration, the first scan chain of each pair is connected to the second scan chain of each pair, and the input terminal of the second scan chain becomes the output terminal. Thereby creating a longer scan chain of the first and second scan chains together with one input terminal and one output terminal. The two loads allow for efficient scanning in the first mode, or debugging to determine the position of a fault in the second mode.

Abstract: A decoding apparatus for decoding digital video data, comprising: a data memory comprising registers, each register being capable of storing a data strings comprising a plurality of data sub-strings such that the data sub-strings are not individually addressable; an input for receiving compressed video information represented by a matrix of data values and loading each data value in order into a respective one of the sub-strings; and processing means for performing an inverse zigzag operation on the matrix of data values by executing a series of reordering operations on the data strings to reorder the data sub-strings comprised therein.

Abstract: A biasing circuit comprising a first switching device having a control terminal, and first and second switching terminals. The first switching terminal being connected to a supply voltage, the second switching terminal being connected through a first resistive element to ground, and the control terminal being supplied by a reference voltage which is determined depending on the mode of operation of the circuit. The circuit further comprising a first branch connected between the control terminal and ground comprising a second resistive element in series with a second switching device. The second switching device forming part of a first current mirror having a second branch for effecting a generated bias value. During a normal mode of operation the reference voltage is dependant on the generated bias value, whereas during a standby mode of operation the reference voltage is connected to a low potential.

Abstract: A privileged data table maintains a list of regions of a memory which contain privileged data. When a data access operation is attempted, a privilege rule enforcer compares the address of the memory being accessed to the list of privileged regions. If the memory address falls within a privileged region, then the memory access operation is blocked unless the instruction accessing the memory has been securely authorized by a code verifier. A privileged instruction table is provided to maintain a list of instructions stored in an instruction list that have been verified. When an instruction is fetched from the instruction list, an instruction privilege identifier compares the instruction with the list of verified instructions, and generates a signal indicating the privilege status of the instruction. Instructions are blocked according to the privilege signal. Only privileged instructions are allowed to modify the privileged data table and the privileged instruction table.