Abstract: An integrated circuit chip comprising embedded digital processor and an on-chip emulation device coupled to said digital signal processor, said emulation device being operable to control said digital processor and to collect information about the operation of said digital processor, the on-chip emulation device having a communication port for off-chip communication, the chip further comprising an on-chip interface having a first port connected to said communication port of said on-chip emulation device and a second port for connection to a non-proprietary bus wherein said interface is operable to convert between a format suitable for said on-chip emulation device and a format suitable for said non-proprietary bus.

Abstract: A debugging system comprising a host computer system and a target device, said target device having an embedded digital processor on an integrated circuit chip, an on-chip emulation device coupled to said digital processor, the on-chip emulation device being operable to control said digital processor and to collect information about the operation of said digital processor, the on-chip emulation device having a communication port operable to receive information from and emit information to the host computer system wherein said debugging system further comprises an interface on said integrated circuit chip having a first port connected to said communication port of said on-chip emulation device and a second port connected to a universal serial bus, said host computer system having a universal serial bus port connected to said universal serial bus wherein said host computer system comprises a proxy server program for managing the universal serial bus port to enable communication over said universal serial bus, a

Abstract: The described embodiments of the invention relate to a voltage reference generator which can be produced using new process technologies and which is still compatible with older designs/products. This is achieved by the introduction of circuitry to generate an offset voltage independently of the main reference voltage generation circuitry.

Abstract: A method for processing a video data stream including a series of pixel values corresponding to pixel sites in an electronic imaging device includes the step of filtering the video data stream in real time to correct or modify defective pixel values based on a plurality of neighboring pixel values. The filtering of each pixel value uses a current pixel value as part of a data set including the neighboring pixel values in determining whether and/or how to correct or modify the current pixel value. The pixel values which are most severely defective are identified and stored. A first filtering algorithm is applied to those pixels whose locations are not stored, and a second filtering algorithm is applied to the most severely defective pixels whose locations have been stored. The filtering algorithm includes sorting the current pixel value and the neighboring pixel values into a rank order and modifying the current pixel value on the basis of its place in the rank order.

Abstract: A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the

Abstract: A computer navigation device includes a movement sensor and a trigger device activated by a timer. The computer navigation device periodically transmits to a host computer a pre-defined signal corresponding with the signal that would otherwise be generated by the movement sensor on detection of specific movements of the computer navigation device.

Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.

Abstract: A method is described for identifying an inaccurate model of a hardware circuit. The method includes the steps of simulating the model of the circuit by applying a plurality of signals, said plurality of signals having at least one abstract data type level to provide a set of expected results, replacing the at least one abstract data type level with two or more levels having different values to thereby provide and expanded set of signals to apply to said model, resimulating the model with said expanded set and comparing the two sets of results and providing an output signal indicating if the model is inaccurate if the results contradict.

Abstract: An embodiment comprises a semiconductor integrated circuit for restricting the rate at which data may be accessed from an external memory by a device coupled to the circuit. The rate of data access is restricted if the data access satisfies one or more conditions. For example, one of the conditions is that the device which is requesting the data is insecure. Another condition is that the requested data is privileged. A data access monitor is provided to monitor data accesses and to is arranged to generate an access signal to indicate whether the conditions are satisfied or not. A bandwidth comparator determines whether data access exceeds a threshold and, if so, the semiconductor integrated circuit is impaired to prevent further data access.

Abstract: A method of rendering a plurality of triangles into a color buffer defined by a plurality of pixel locations, utilizing a triangle identification buffer and a depth buffer. A relatively unique identifier is assigned to each of the triangles to be rendered. Before color and texture mapping, each triangle is depth compared on a per pixel basis. If a pixel of a current triangle is in front of any existing pixel at that point, the current triangles identifier is over-written into a triangle identification buffer. Color texture data is only retrieved for each triangle that appears in the identification buffer once all triangles have been compared.

Abstract: There is disclosed a method of communicating with an integrated circuit chip having plural components thereon, the components including digital processing circuitry and an on-chip emulator connected to the digital processing circuitry for initiating command and control sequences for the digital processing circuitry in response to externally applied signals or in response to detected states of the digital processing circuitry.

Abstract: The present invention is directed to methods for verifying adequate synchronisation of signals that cross clock environments. According to one exemplary method, a circuit under design includes a plurality of functional elements and a plurality of clock environments, and has one or more signals passing from one clock environment to another therein. The method includes the steps of (i) modelling at least one of the functional elements to have an unknown state as an output for a predetermined time after a timing event of a clock signal, (ii) simulating the circuit, and (iii) determining which functional element is a synchroniser to thereby identify if there is a synchronisation problem for a signal passing from one clock environment to another.

Abstract: A circuit for maintaining a generated reference voltage at a substantially constant level for a range of temperatures. The circuitry comprising: a first circuit arranged to generate a first voltage having a first temperature characteristic, and a second circuit arranged to generate a second voltage having a second temperature characteristic. The second voltage compensates for the first voltage to maintain the reference voltage at a substantially constant level over a first temperature range. The circuit also having a third circuit arranged to act in a second temperature range to compensate for the first voltage to maintain the reference voltage at a substantially constant level in the second temperature range.

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract: A host computer has a file with a subroutine required for operation of an application on a target. The file is dynamically loaded to memory of the target, whereby the file has an entry point at a dynamically-determined location. Data representative of the address of the entry point is stored in memory at a predetermined location. The application is then run on the target, causing the application to determine the entry point, thereby accessing the subroutine and allowing the subroutine to run.

Abstract: A method of operating a computer system to design an application specific processor (ASP) comprises defining a set of peripherals for the ASP which are responsive to stimuli and which communicate with a processor, generating for each peripheral an input file which defines the functional attributes of that peripheral in a high level language with an input data structure, entering the input file into the computer system and operating a modelling tool loaded on the computer system to generate from the input file a register definition file by allocating specific elements of the input data structure to predefined sectors of a register definition table, and using the register definition file to create in silicon the registers of the ASP.

Abstract: A system and method for verifying the authenticity of instructions retrieved from a memory for execution by a processor. In one embodiment, an instruction monitor monitors execution parameters associated with the retrieved instruction and resets the system in response to an indication that an instruction is not authentic.

Abstract: A programmable flip-flop is presented for outputting data. The flip-flop includes a first latch for latching a first input value in response to a rising edge of a clock signal. A second latch latches a second input value in response to a falling edge of the clock signal. A selection function controlled by the clock signal selectively supplies outputs of the first and second latches to the input of a third latch. A control circuit for the third latch accepts as inputs the clock signal and an inverted clock signal. The programmable flip-flop is configurable to operate in at least first and second modes selectable by the selection function and third latch control circuit, such that in the first mode the output of the third latch is the first and second input values multiplexed together and output at twice the clock rate.

Abstract: A method of forming an executable program from a plurality of object code modules, each object code module comprising section data and relaxation instructions, at least one of said object code modules comprising a library module of predefined section data and relaxation instructions, the executable program to be run on a target processor having a selected endianness, the method comprising in response to a relaxation instruction, loading a library module into temporary storage; retrieving the value of a first variable, said first variable denoting the selected endianness of the target processor; comparing the value of said first variable with the endianness of the section data and relaxation instructions of the library module; in response to the result of the comparing step not being a match, converting the endianness of the section data of the library module to that of said first variable; processing the relaxation instructions and converted section data to form part of the executable program.

Abstract: A current source, adapted to generate a current proportional to absolute temperature has a greatly reduced supply voltage dependence and is still able to operate at low operating voltages. This is achieved by the incorporation of a compensation resistor through which a start-up current is passed.