Abstract: A device for generating a regulated DC voltage from a DC power supply voltage source includes a loop formed by a reference voltage generator powering an operational amplifier. The output of the operational amplifier powers the input to the reference voltage generator.

Abstract: A conveyor support for integrated circuits in an on-line oven, including a mechanism for driving and guiding the elements to be soldered while maintaining a lower surface of one of said elements in direct contact with a wall of the oven.

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a semiconductor substrate having a lower portion on top of which there is an upper layer that is more heavily doped than the lower portion. A first block and a second block are produced in the upper part of the substrate, and decoupling means are arranged in the vicinity of the first block. The decoupling means include at least one decoupling circuit that is connected to the lower portion of the substrate and to a ground connection pad, and the decoupling circuit has a minimum impedance at a predetermined frequency. In one preferred embodiment, the decoupling circuit includes an inductive-capacitive resonant circuit having a resonant frequency substantially equal to the predetermined frequency.

Abstract: A regulation circuit for regulating an output voltage of a positive charge pump for an integrated circuit includes a comparison circuit receiving a reference voltage at an input, and delivering an enabling signal at an output to the positive charge pump. The regulation circuit further includes a first switching circuit controlled by a first control signal for the application of a first voltage level as a reference voltage when the integrated circuit is in an operational mode, and the application of a second voltage level as the reference voltage when the integrated circuit is in a standby mode.

Abstract: A modular arithmetic coprocessor comprises a circuit for the computation of an error correction parameter H=2x mod N associated with the Montgomery method. This computation circuit comprises a first register, a second register, and a first circuit for the series subtraction of either zero, N, twice N, or three times N from the contents of the first register. A multiplication circuit carries out a multiplication by four. A second circuit compares the result with N, twice N or three times N.

Abstract: The invention provides a method of forming conductive members in an integrated circuit comprising the steps of depositing a first dielectric layer on a substrate; depositing a first conductive layer; depositing a second dielectric layer; forming cavities extending at least partially through the first dielectric layer; forming a second conductive layer on internal surfaces of the cavities; and electrolytically depositing another conductive material within the cavities.

Abstract: The present invention relates to a circuit for controlling a fluorescent lamp, including circuitry that provides a low frequency alternating current to the fluorescent lamp, this circuitry being controlled by a controllable switched-mode current source operating at high frequency.

Abstract: The microcontroller accesses a battery of hidden registers used essentially in the field of emulation. The fact that there is a large number of hidden registers means that it is not possible to assign them an address by which they can be accessed directly. Since this battery of hidden registers has to be accessible by a host circuit and by a microprocessor, recourse is had to a method of indirect addressing by means of two peripheral control registers. A priority signal obliges the microprocessor to wait for the read and write resources to be released by the host circuit to perform these instructions.

Abstract: A remanent, electrically programmable and erasable, memory device comprises of a MOS type transistor whose gate insulator contains charged mobile species is disclosed. The gate insulator is comprised transversely of a sandwich comprising at least five areas. Two intermediate areas have first band-gap values, and two endmost and a central areas have band gap values greater than the first values.

Abstract: A capacitor integrated on a silicon substrate includes a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon and a silicide layer covering the second electrode. The second electrode has a high dopant concentration at its interface with the silicon oxide layer and a low or medium dopant concentration at its interface with the silicide layer.

Abstract: A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.

Abstract: A voltage regulation device is provided for receiving a voltage at an input node and supplying a regulated voltage to electronic circuitry at an output node. The device includes a switching circuit that is coupled between the input node and the output node, and a control circuit that is coupled to the switching circuit. When the voltage level at the output node is below a threshold voltage, the control circuit controls the switching circuit so as to substantially short-circuit the input node and the output node. On the other hand, when the voltage level at the output node is not below the threshold voltage, the control circuit controls the switching circuit so as to substantially isolate the input node from the output node. In a preferred embodiment, the switching circuit includes an NMOS transistor, and the control circuit includes a differential amplifier that supplies a control signal to the gate of the NMOS transistor. A smart card containing a voltage regulation device is also provided.

Abstract: A device for two-way digital transmission on a bus having at least one two-way line. The device includes a first pulling device for pulling a first section of the line to a first logic level, a second pulling device for pulling a second section of the line to the first logic level, and at least one two-way repeater that is connected between the first section and the second section. The repeater includes a third pulling device for pulling the first section of the line to a second logic level, a fourth pulling device for pulling the second section of the line to the second logic level, and a logic circuit that prevents the third and fourth pulling devices from being simultaneously active. In one preferred embodiment, at least one electronic circuit is connected to the first section of the line and at least one other electronic circuit is connected to the second section of the line.

Abstract: The present invention relates to a switchable d.c. voltage regulation circuit having an input terminal, an output terminal, a reference terminal, and a control terminal, including a gate turn-off thyristor, the main terminals of which are connected to the input terminal and to the output terminal, respectively; a resistor connected between the input terminal and the cathode gate of the thyristor; a transistor, the main terminals of which are connected to the cathode gate of the thyristor and to the reference terminal, respectively; and an avalanche diode connected between the output terminal and the base of the transistor.

Abstract: The present invention relates to a DRAM circuit including a plurality of memory cells organized in an array, including switches for associating with each end of each column of the array at least two latches controlled independently from each other to store data written into or read from the considered column.

Abstract: An activation signal generating circuit includes a combinational logic circuit and a switch. The combinational logic circuit receives a normal mode control signal and a test mode control signal, and the switch receives a periodic clock signal. The switch is controlled by the output of the combinational logic circuit such that an activation signal is generated from the periodic clock signal. In one preferred embodiment, the switch is a CMOS change-over switch having two complementary MOS transistors connected in parallel, and a potential setting circuit imposes a specified potential at the output of the switch when the switch is open. A method of generating an activation signal is also disclosed.

Abstract: A method for testing decoding circuits in a memory including a matrix of storage cells includes writing the same first word in all the storage cells, and then writing second words in the matrix such that each row and each column has at least one stored second word. The second words are different from the first words. If several second words are written in the same row or in the same column, then the second words are different from one another. Reading all the words in the memory permits verification of the integrity of the decoding circuits, and reduces the testing time of the memory.

Abstract: The invention relates to a test area of an electronic circuit comprising a contact point formed in the surface of a substrate. The test area also includes spaced apart radially extending bosses adjacent the contact point for guiding a test probe positioned on the surface of the substrate to the contact point.

Abstract: A division method and division circuit that can be integrated into a modular arithmetic coprocessor performs a reversal by word for the dividend and the quotient. This is done using a plurality of registers.

Abstract: A DRAM made in monolithic form, the cells of which each include a MOS transistor and a capacitor, a second electrode of which is common to all cells of a same row and is covered with an insulator, the insulator being coated with independent conductive elements distributed on a same horizontal plane, two neighboring elements being biased to respective high and low levels.