Abstract: A multiplication circuit with an accumulator is provided. The multiplication circuit includes first latch circuits, second latch circuits, and elementary adders that are cascade-coupled to one another in series through the first latch circuits. Each of the adders has its carry output coupled to one of its inputs through one of the second latch circuits. Additionally, cancellation circuitry cancels the contents of each of the second latch circuits at least during selected multiplication operations so as to carry out multiplication operations in a Galois field. In some preferred embodiments, the cancellation circuitry includes a logic gate that receives a selection signal indicating the mode of operation, and the logic gate sets and holds the second latch circuits at zero when the selection signal indicates that the multiplication operation is to be done in a Galois field.

Abstract: A system and method for detecting the nature of a video signal using a video synchronization circuit including a phase locked loop having a time constant is disclosed. The method includes calculating a horizontal phase difference between a predetermined first line of the video signal and a predetermined second line of the video signal, the predetermined first line and the predetermined second line bracketing a change of frame. If the horizontal phase difference is greater than a threshold, the video signal is deemed to be a video recorder signal. The method further includes adjusting the time constant of the phase locked loop of the video synchronization circuit according to the nature of the video signal, as determined in the calculating step.

Abstract: A method and apparatus for controlling a brushless motor having a plurality of windings switched through a sequence of steps includes determining a transition time from one step to the next. The transition time is determined by detecting a zero crossing of a back emf in one of the plurality of windings. A delayed time to be added to the transition time is determined wherein the delayed time is selected according to the step in the sequence of steps being executed and is dependent on the duration of one of a preceding interval between zero crossings. A delay time proportional to a duration of a last shortest interval is supplied to follow a longest interval. A delay time proportional to a duration of a last longest interval is supplied to follow a shortest interval and a delay time proportional to a duration of a medium interval is supplied to follow a medium interval. The method may be used, for example, with a star or delta connected motor having any number of windings.

Abstract: A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide layer. A trench crosses the P-type epitaxial layer and penetrates into at least a portion of the height of the N-type epitaxial layer beyond the periphery of the active area. The doping level of the P-type epitaxial layer is chosen so that, for the maximum voltage that the diode is likely to be subjected to, the equipotential surfaces corresponding to approximately ¼ to ¾ of the maximum voltage extend up to the trench.

Abstract: A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas; forming a spacer along the side of the opening, this spacer having a rear portion against said border and an opposite front portion; opening the protective and covering layers behind the rear portion of the spacer; and removing the protection layer to reach the rear portion of the spacer; whereby two self-aligned areas are defined on either side of the spacer length.

Abstract: The invention concerns a control circuit for controlling a load to be supplied in alternating current voltage, comprising a two-way switch capable of being controlled by phase angle, in series with the load between two terminals applying the alternating current supply, and comprising, in parallel with the switch, a first resistive element, a first capacitor and an element, in series with the first resistive element and the first capacitor, and operating, in steady state conditions, as a constant current source, the midpoint of the association in series connection of the first resistive element and the first capacitor being connected, via an element with two-way conduction automatically triggered when the voltage at its terminals exceeds a predetermined threshold, to a terminal controlling the switch.

Abstract: A protection device includes a switching transistor (M11), connected between the gate of the output transistor (TS1) and ground, and a control circuit (CM), connected to the gate of the switching transistor (M11), which are capable of ensuring that the switching transistor (M11) is off when there is no electrostatic discharge at the drain of the output transistor (TS1) and capable of turning the switching transistor (M11) on when there is an electrostatic discharge at the drain of the output transistor (TS1).

Abstract: An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.

Abstract: A method for estimating the frequency error of a demodulator for restoring two binary signals carried on two carriers of same frequency but in phase quadrature, including the steps of forming vectors having as components the successive couples of values of the two binary signals; applying to each vector a transform which multiplies by four its angle at least when it is equal to a multiple of &pgr;/4 and which substantially preserves its module; and calculating the average of the transformed vectors. The frequency error is obtained as being the derivative of the angle of the average vector.

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract: The present invention relates to a read amplifier (SA2) comprising a read stage (RDST), a reference stage (RFST) and a differential output stage comprising PMOS and NMOS type transistors. According to the present invention, the transistors of the differential stage (DIFST2) comprise only one PMOS transistor (TP3) and one NMOS transistor (TN3) in series, the PMOS transistor (TP3) having its gate linked to one node of the read stage (RDST), the NMOS transistor (TN3) having its gate linked to one node of the reference stage (RFST), the mid-point of the PMOS and NMOS transistors of the differential stage forming a data output node (DATAOUT) of the read amplifier. The read amplifier according to the present invention has the combined advantages of a short read time and a low electrical consumption. Application to EPROM, EEPROM and FLASH type non-volatile memories.

Abstract: An input stage for a video receiver includes a variable gain amplifier, an analog-to-digital converter for sampling a video signal and a digital processing unit for processing digital samples of the video signal. An analog regulating circuit sets an input potential at an input of the variable gain amplifier. A differential architecture is used for the variable gain amplifier and the digital analog converter. A conversion circuit between an input coupling capacitor and the variable gain amplifier allows generating the video signal on two channels in antiphase, which are centered on the common mode voltage. Such differential architecture allows reducing the amplitude of analog signals, which is particularly advantageous in the case of a low voltage supply delivering a few volts. In addition, linearity of the video signal processing is enhanced.

Abstract: A mirroring circuit operating at high frequencies is provided. The mirroring circuit includes a first branch having a first transistor in series with a first resistor, a second branch having a second transistor in series with a second resistor, and a servo circuit for controlling current flowing in the first branch and the second branch. The servo circuit includes a third transistor configured as a diode, a source of the third transistor coupled to a source of the first transistor, a fourth transistor configured as a shift lever, a source of the fourth transistor coupled to ground via a third resistor, a fifth transistor configured as a diode, a source of the fifth transistor coupled to a source of the second transistor, and a sixth transistor configured as a shift lever, a source of the sixth transistor coupled to ground via the third resistor.

Abstract: A power supply circuit receiving several supply voltages on respective switches, at least one of the switches being a first PMOS transistor connected between one of the supply voltages and a common output terminal, this switch being associated with a second PMOS transistor connected between the gate of the first transistor and a power supply node maintained at the highest of the other supply voltages, with a third NMOS transistor, which is less conductive in the on state than the second transistor, connected between the gate of the first transistor and the ground, and with a fourth PMOS transistor having its source connected to the power supply line of the switch and its drain connected to ground via a current source, and to the gates of the second, third, and fourth transistors.

Abstract: An electrically erasable and programmable memory (EEPROM) includes a memory array containing memory cells connected to word lines arranged in rows and to bit lines arranged in columns. The memory array includes a first special zone for storing special bits of a first type, and a second special zone for storing special bits of a second type. The first special zone includes a first row of memory cells connected to a first word line, wherein N1 memory cells are connected to N1 bit lines of a determined column of the memory array. The second special zone includes a second row of memory cells connected to a second word line, wherein N2 memory cells are connected to N2 other bit lines of the determined column. The N1 bit lines are not connected to the second row of memory cells, and the N2 bit lines are not connected to the first row of memory cells.

Abstract: The present invention relates to a processor including at least one memory access unit for presenting a read or write address over an address bus of a memory in response to the execution of a read or write instruction; and an arithmetic and logic unit operating in parallel with the memory access unit and arranged at least to present data on the data bus of the memory while the memory access unit presents a write address. The processor includes a write address queue in which is stored each write address provided by the memory access unit waiting for the availability of the data to be written.

Abstract: The present invention relates to a data processing system comprising a processor provided with two memory access units operating in parallel; two separate memories respectively associated with the two access units; and circuitry for, when the address of a datum to be written into a memory is in a predetermined address range, writing the datum into both memories at the same time at the same address.

Abstract: A dynamic memory circuit including memory cells arranged in an array of rows and columns, each row capable of being activated by a word line and each column being formed of cells connected to a first and to a second bit lines, which includes at least one, spare row formed of static memory cells, adapted to being activated to replace a memory cell row, each spare cell being connected to the first and second bit lines of a column of the circuit.

Abstract: A microprocessor includes internal registers, an arithmetic and logic unit, and reads a program memory and executes an instruction set stored therein. The instruction set includes at least one instruction for exchanging the contents of both memory locations. The microprocessor includes an additional internal register connected to an output of the arithmetic and logic unit, and transfers the contents of a first one of the memory locations to be exchanged into the additional register when executing the instruction set. The microprocessor further transfers the contents of a second one of the memory locations to be exchanged into the first memory location, and transfers the contents of the additional register into the first memory location.

Abstract: A detection device includes an antenna for receiving an incident signal, and for delivering a base signal. A comparator receives the base signal and provides an intermediate signal representative of the sign of the base signal relative to a reference signal. A sampling circuit samples the intermediate signal for providing a digital signal. A digital processing circuit correlates the digital signal with a predetermined correlation signal.