Patents Assigned to STMicroelectronics S.A.
  • VOLTAGE REGULATOR INCORPORATING A STABILIZATION RESISTOR AND A CIRCUIT FOR LIMITING THE OUTPUT CURRENT
    Publication number: 20030085693
    Abstract: A voltage regulator includes a power transistor for providing an electrical current to a load circuit connected to an output of the regulator. The delivered current is limited by a limitation circuit within the regulator. A stabilization resistor is connected between the power transistor and the output of the regulator. The limitation circuit includes a fixed-voltage generator, and a comparator for comparing the voltage generated in the stabilization resistor by the output current of the regulator with the fixed voltage. The output of the comparator controls an adjustment transistor that limits the current delivered by the power transistor.
    Type: Application
    Filed: September 24, 2002
    Publication date: May 8, 2003
    Applicant: STMicroelectronics S.A.
    Inventor: Nicolas Marty
  • Insulating wall between power components
    Patent number: 6559515
    Abstract: An insulating wall of a second conductivity type intended for separating elementary components formed in different wells of a semiconductive layer of a first conductivity type, a component located in one at least one of the wells being capable of operating with a high current density. The insulating wall includes at least two elementary insulating walls separated by a portion of the wafer material and, in operation, this portion is connected to a reference potential.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: May 6, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Franck Duclos
  • Fast digital adder
    Patent number: 6560625
    Abstract: A carry look-ahead digital adder that adds a first operand A of n bits and a second operand B of n bits, with n=2m, including: a first block calculating couples of signals Pq and Gq from the bits of rank q, Aq and Bq, of the first and second operand, with Pq=Aq+Bq and Gq=Aq•Bq; and a second block formed of a regular array of elementary cells of identical functions arranged in n rows and m columns, and elementary cells having two couples of inputs {E1, E2} and {E3, E4} and one couple of outputs {O1,O2}, providing O1=E1•E3 and O2=E2•E4+E3; the elementary cells being interconnected to optimize the propagation speed of the internal signals along a tree-like path.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: May 6, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Stéphane Rossignol, Pierrette Faucherand
  • Process and device for synchronizing a reference signal with respect to a video signal
    Publication number: 20030081149
    Abstract: A synchronization process may include detecting successive horizontal synchronization pulses of a video signal, and a phase comparison between the successive detected pulses and the successive transitions of the reference signal for controlling the oscillator of the phase-locked loop. The detection of each horizontal synchronization pulse may include sampling the video signal, low-pass filtering the sampled signal, thresholding the filtered signal for leaving pulses having a level below a threshold. The synchronization process may also include selecting, as a function of predetermined selection criteria, from among the residual pulses within an observation window centered on a transition of the reference signal for the one which corresponds to the horizontal synchronization pulse.
    Type: Application
    Filed: October 25, 2002
    Publication date: May 1, 2003
    Applicant: STMicroelectronics S.A.
    Inventor: Diego Coste
  • Method and device for detecting the parity of successive fields of an interlaced video signal
    Publication number: 20030081148
    Abstract: Successive values of a horizontal phase of a video signal are determined a predetermined integer number of video lines after the successive occurrences of vertical synchronization pulses. The successive values of a parity bit are updated according to the successive values of the horizontal phase. Indications on the parity of the fields are provided from the successive values of the parity bit.
    Type: Application
    Filed: October 29, 2002
    Publication date: May 1, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Diego Coste, Ilija Materic, Francois Besson, Herve Maffini
  • Photocell incorporating a lightguide and matrix composed of such photocells
    Publication number: 20030081895
    Abstract: A photocell having an entry face for the light and a photosensitive element, as well as to a matrix composed of such photocells. A lightguide-forming element placed between the entry face and the photosensitive element of the photocell ensures optical coupling between the latter two components. It makes it possible to place on either side of the photosensitive element electronic components for reading and for controlling the photocell, while reducing the loss of light incident on the entry face corresponding to the rays which would strike these electronic components. This lightguide-forming element is composed of at least three dielectric materials having different respective optical refractive indices and placed within concentric volumes.
    Type: Application
    Filed: September 18, 2002
    Publication date: May 1, 2003
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Francois Roy, Thierry Devoivre, Yann Marcellier
  • Circuit for shifting switching signals
    Patent number: 6556047
    Abstract: A circuit for shifting at least one input switching signal includes a CMOS bistable circuit having two branches, and a circuit for accelerating the switching of the bistable circuit. The circuit for accelerating the switching allows an output transistor of each branch to be switched to the off state when an input transistor of the branch switches to the on state. The circuit for accelerating switching includes, for at least one given branch, an associated current mirror generating a turn-off current for the output transistor of the branch on the basis of a turn-on current for the input transistor of the branch.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: April 29, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Pascal Debaty
  • Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor
    Patent number: 6555482
    Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: April 29, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Malgorzata Jurczak, Michel Haond
  • Low consumption oscillator
    Patent number: 6556092
    Abstract: A low consumption oscillator having an inverter connected to a high supply potential and to a low supply potential via two respective resistors, with the resistors formed of capacitors having strong leakages.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: April 29, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Richard Ferrant
  • Computer memory access
    Patent number: 6553478
    Abstract: A memory for a computer system that includes a plurality of memory banks which provide an interleaved memory region as well as X and Y memory regions. Each memory access address includes a most significant set of bits indicating which of the interleaved, X, or Y memory regions is to be accessed. Each memory access address also includes a least significant set of bits indicating an address within the bank of the access region. At least one bit in the least significant set is a bank selector and one bit of the most significant set of bits is an X or Y region selector.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: April 22, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Nicolas Grossier
  • Process for fabricating a self-aligned vertical bipolar transistor
    Patent number: 6551891
    Abstract: The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window, so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: April 22, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Alain Chantre, Michel Marty, Helene Baudry
  • Etching an organic material layer, particularly for producing interconnections of the damascene type
    Patent number: 6551930
    Abstract: A method for etching an organic dielectric material layer includes depositing an inorganic barrier layer on the organic dielectric material layer, and depositing an inorganic masking layer on the inorganic barrier layer. A masking resin layer is deposited on the inorganic masking layer. The method further includes patterning the masking resin layer and etching through the inorganic masking layer to expose the inorganic barrier layer. Remaining portions of the masking resin layer are removed, and the exposed inorganic barrier layer is etched to expose the organic dielectric material layer. The method further includes removing remaining portions of the inorganic masking layer, and etching the exposed organic dielectric material layer while using the inorganic barrier layer as a mask.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: April 22, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Françoise Vinet, Yves Morand
  • Vertical power component manufacturing method
    Patent number: 6551868
    Abstract: A method for manufacturing a vertical power component on a silicon wafer, including the steps of growing a lightly-doped epitaxial layer of a second conductivity type on the upper surface of a heavily-doped substrate of a first conductivity type, the epitaxial layer having a thickness adapted to withstanding the maximum voltage likely to be applied to the power component during its operation; and delimiting in the wafer an area corresponding to at least one power component by an isolating wall formed by etching a trench through the epitaxial layer and diffusing from this trench a dopant of the first conductivity type of high doping level.
    Type: Grant
    Filed: November 2, 2000
    Date of Patent: April 22, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Gérard Auriel, Laurent Cornibert
  • Biasing of a mixer
    Patent number: 6552586
    Abstract: A mixer including a stage for inputting a voltage signal to be shifted and a shift and output stage for providing frequency-shifted signals, a biasing network of the output stage including, between a high supply and a biasing node, a constant current source in parallel with an output element of a current mirror, an input element of which receives a bias order from the input stage.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: April 22, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Jean-Charles Grasset, Philippe Cathelin, Kuno Lenz
  • Class AB amplifier circuit
    Publication number: 20030071687
    Abstract: A class AB amplifier circuit includes a complementary output stage and a biasing circuit for biasing the output stage. The complementary output stage includes a P-type MOS transistor and an N-type MOS transistor, and the biasing circuit includes a bipolar transistor. The emitter and collector of the bipolar transistor are respectively connected to the gates of the P-type and N-type MOS transistors. The bipolar transistor is biased for controlling a bias voltage between the respective gates of the P-type and N-type MOS transistors.
    Type: Application
    Filed: September 17, 2002
    Publication date: April 17, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Marius Reffay, Michel Barou
  • Method and circuit of digital measurement of the phase of a sinusoidal signal
    Publication number: 20030072361
    Abstract: A method for measuring with a maximum error E the phase of a substantially sinusoidal signal, of angular frequency &ohgr;=2&pgr;/T, sampled with a sampling period T/r, in which the phase is calculated as the time at which a straight line crossing two consecutive samples located on either side of a median value of the signal reaches said value, including the step of selecting number r from a range included between a value r0 and a value equal to from two to three times value r0, such that: 1 E ≥ max t ∈ [ - T r0 , 0 ] ⁢ [ t - T r0 · round ⁡ ( G · sin ⁢   ⁢ ω ⁢   ⁢ t ) round ⁡ ( sin ⁡ [ G · ω · t + 2 ⁢ π r0 ] ) - round ⁡ ( G · sin ⁢   ⁢ ω ⁢   ⁢ t ) ]
    Type: Application
    Filed: October 16, 2002
    Publication date: April 17, 2003
    Applicant: STMicroelectronics S.A.
    Inventor: Patrick Simeoni
  • Threshold amplifier
    Patent number: 6549048
    Abstract: A threshold amplifier receives a logic supply voltage and a ground voltage and includes a Schmitt trigger comprising an inverter stage and a hysteresis stage connected to the inverter stage for setting a high and a low hysteresis threshold. A disabling circuit disables the hysteresis stage as a function of a level of the logic supply voltage. The threshold amplifier further includes a detection circuit for detecting the level of the logic supply voltage with respect to a detection threshold, and for activating the disabling circuit for disabling the hysteresis stage when the level of the logic supply voltage is below the detection threshold.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: April 15, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: François Tailliet
  • Electromagnetic transponder operating in very close coupling
    Patent number: 6547149
    Abstract: An electromagnetic transponder of the type including an oscillating circuit upstream of a rectifier adapted to providing a D.C. supply voltage to an electronic circuit, the electronic circuit including circuitry for transmitting digitally coded information, and the transponder including circuitry for detuning the oscillating circuit with respect to a determined frequency, the circuitry for detuning the oscillating circuit being used when the transponder has to transmit information while it is very close to a read/write terminal.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: April 15, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Luc Wuidart, Michel Bardouillet, Jean-Pierre Enguent
  • Audio amplifying circuit
    Publication number: 20030067350
    Abstract: An amplifying circuit receiving an input voltage and a reference voltage equal to a fraction of the circuit supply voltage, the reference voltage provided by a time constant circuit, including a circuit for, upon power-on, inhibiting the amplifying circuit for as long as the difference between the value of the provided reference voltage and the voltage at the output of the time constant circuit is greater than a determined threshold.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 10, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Frederic Goutti, Christophe Forel
  • Capacitor integration
    Patent number: 6544841
    Abstract: A capacitor having an electrode with a general cup shape, including a generally horizontal bottom and vertical walls, and in electric contact by its bottom with a conductive pad, the pad extending beyond the upper surface of an insulating layer and the bottom including a complementary recess of the protruding pad portion.
    Type: Grant
    Filed: February 11, 2000
    Date of Patent: April 8, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Jérôme Ciavatti