Abstract: A receiver of a frequency-modulated signal representing a digital signal includes a down conversion unit or frequency translation unit to lower the frequency of the frequency-modulated signal and a digital demodulator to regenerate the digital signal from the lowered-frequency signal. The receiver furthermore includes a counter circuit to determine the number of periods of a reference signal from the frequency translation unit during a period of the lowered-frequency signal. The digital demodulator includes a computer unit to compute the period of the lowered-frequency signal from the number of periods of the reference signal.

Abstract: The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.

Abstract: An integrated temperature sensor delivers threshold detection signals when temperature thresholds have been exceeded. The temperature sensor includes a circuit for detecting a first temperature threshold having a first detection threshold, and for detecting a second temperature threshold having a second detection threshold. The circuit also detects a third temperature threshold between the first and second temperature thresholds, and detects a fourth temperature threshold between the first and second temperature thresholds. The third temperature threshold has a third detection threshold linked with the first detection threshold so that a deviation of the first detection threshold causes a corresponding deviation of the third detection threshold. Similarly, the fourth temperature has a fourth detection threshold linked with the second detection threshold so that a deviation of the second detection threshold causes a corresponding deviation of the fourth detection threshold.

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

Abstract: A monolithic component including two thyristors of a composite bridge connected to an A.C. voltage terminal by a common terminal corresponding to a common rear surface metallization forming an electrode of opposite biasing of each thyristor. An isolating wall separates a substrate in two portions, a first portion includes on its lower surface side an anode region and on its upper surface side a cathode region, the second portion includes on its lower surface side a cathode region and on its upper surface side an anode region. The isolating wall surrounding each of the components extending towards the main electrode on the side which carries no common metallization and including in this extended region an N-type area, the two areas being connected together to a common control terminal.

Abstract: A power component formed in an N-type silicon substrate delimited by a P-type wall, having a lower surface including a first P-type region connected to the wall, and an upper surface including a second P-type region, a conductive track extending above the substrate between the second region and the wall. The component includes a succession of trenches extending in the substrate under the track and perpendicularly to this track, each trench being filled with an insulator.

Abstract: A control method and a linear regulator of the type including a power MOS transistor, controlled by a differential amplifier having a first input terminal receiving a reference voltage and a second input terminal receiving, via a switchable resistor circuit, the output voltage of the regulator, a smooth switching of the resistors being provided.

Abstract: A touch-sensitive detector includes a detection surface and a conducting element, and a first and second set of electrodes, each set of electrodes including at least one electrode extending parallel to the detection surface and where each electrode is electrically isolated. A first and second interaction capacitor is formed by the conducting element with the first and second set of electrodes, respectively. The second interaction capacitor has a lower capacitance than the first interaction capacitor. The touch-sensitive detection element further includes a first and second set of detectors arranged for detecting a signal emitted by at least one electrode of the first set of electrodes and the second set of electrodes, respectively, and transmitted through an external element located at the electrode emitting the signal. The external element contacts the detection surface. A touch sensitive detection method is also provided.

Abstract: An amplifier including first, second, and third series-connected stages, the third stage including a MOS output transistor having its source or drain forming an output terminal of the amplifier, including means for detecting the transition from a first operating state of the output transistor in which the drain current varies little with the voltage between the drain and the source to a second state in which the drain current varies substantially proportionally to the voltage between the drain and the source; and means for, upon detection of such a transition, having the voltage gain of the amplifier and/or the product between the bandwidth of the amplifier and the voltage gain of the amplifier at the upper limit frequency of the bandwidth drop.

Abstract: Method of compressing a digital image signal in which a first quantization step set, which is unique for a given segment, is determined so that the number of bits needed to encode the quantized data corresponding to this segment is greater than a target value. This first quantization step set then being modified, as a priority, for the blocks of the segment for which the gain, in the course of this modification, on the reduction of the number of bits needed to encode the quantized data corresponding to the segment to which it belongs, is the highest. This modification is carried out, on as many blocks as is necessary for the number of bits of this segment to be less than or equal to the target value. Device to implement this method.

Abstract: An integrated circuit receives as supply voltages a ground reference voltage, a logic supply voltage and a high voltage. A protection device is associated with at least one gate oxide circuit element. The protection device applies to a supply node of the circuit element either the logic supply voltage under normal conditions of operation of the integrated circuit, or the high voltage under abnormal conditions of operation of the integrated circuit for breaking down the gate oxide.

Abstract: The protection device for an interconnection line of an integrated circuit includes a charge flow-off device connected between the interconnection line to be protected and the substrate of the integrated circuit. The protection device also includes a dummy interconnection line ANT to activate the flow-off device. The protection device is active throughout the manufacture of the integrated circuit.

Abstract: A method for manufacturing a vertical power component on a substrate formed of a lightly-doped silicon wafer, including the steps of boring on the lower surface side of the substrate a succession of holes perpendicular to this surface; diffusing a dopant from the holes, of a second conductivity type opposite to that of the substrate; and boring similar holes on the upper surface side of the substrate to define an isolating wall and diffuse from these holes a dopant of the second conductivity type with a high doping level, the holes corresponding to the isolating wall being sufficiently close for the diffused areas to join laterally and vertically.

Abstract: An integrated static random access memory device includes four transistors and two resistors defining a memory cell. The four transistors are in a semiconductor substrate and are mutually interconnected by a local interconnect layer. The local interconnect layer is under a first metal level and a portion of the local interconnect layer defines above the substrate a base metal level. The two resistors extend in contact with a portion of the local interconnect layer between the base metal level and the first metal level.

Abstract: A vertical voltage-controlled bidirectional monolithic switch formed between the upper and lower surfaces of a semiconductor substrate surrounded with a peripheral wall, including: a first multiple-cell vertical IGBT transistor extending between a cathode formed on the upper surface side and an anode formed on the lower surface side; and a second multiple-cell vertical IGBT transistor extending between a cathode formed on the lower surface side and an anode formed on the upper surface side, in which the cells of each transistor are arranged so that portions of the cells of a transistor are active upon operation of the other transistor.

Abstract: A method for resetting a microcontroller includes a reset sequence to make the microcontroller go from a power-off mode to a run mode when the level of a supply voltage goes over a threshold. The reset sequence includes reading an option word stored in a programmable memory by the user for configuring internal circuits of the microcontroller, particularly circuits that are effected by the reset sequence.

Abstract: A voltage regulator includes a power transistor for providing an electrical current to a load circuit connected to an output of the regulator. The delivered current is limited by a limitation circuit within the regulator. A stabilization resistor is connected between the power transistor and the output of the regulator. The limitation circuit includes a fixed-voltage generator, and a comparator for comparing the voltage generated in the stabilization resistor by the output current of the regulator with the fixed voltage. The output of the comparator controls an adjustment transistor that limits the current delivered by the power transistor.

Abstract: A machine for testing electronic components or chips formed in a wafer (3) and each comprising a multiplicity of electrical connection pads formed on the surface of the wafer, which machine includes a test head (5) having a multiplicity of electrical connection test prods (11) and a mechanism for moving the wafer to be tested with respect to the head so as to bring the ends of the test prods into contact with the pads of each chip, in succession. The test head (5) carries heating and temperature-regulating elements (18) thermally coupled to the electrical connection test prods (11). Preferably, the test head (5) includes a metal block (16) thermally coupled to the electrical connection test prods (11). The heating and temperature-regulating elements (18) are thermally coupled to the metal block.

Abstract: The present invention relates to a method of thinning of a single-crystal silicon wafer so that the wafer has a final thickness lower than 80 &mgr;m.

Abstract: The invention concerns an instructions sequencer for microprocessor wherein the sequencer presents an architecture, a circuit conception and a presents that improves the compacity and facilitates conception and adaptation operations to different instructions sets, the sequencer having a line and column architecture and very widely produced in the form of a transistor and capacitor matrix, functioning with decoding transistors, preload transistors and a matrix for defining the phases of operating cycles.