Abstract: An electronic device may include a transducer configured to generate an electrical output responsive to an input, and a data storage element configured to change state responsive to the transducer. The electronic device may include a power circuit configured to turn on and supply power responsive to the data storage element changing state, and a processing circuit configured to be powered by the power circuit.

Abstract: A phase-change memory device, comprising: a memory array of PCM cells, a variable current generator, and a sense amplifier. The current generator comprises a reference array of PCM cells programmed in SET resistance state. The phase-change memory device further comprises a decoder for addressing each cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; and a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current to be lower than said mean value.

Abstract: A structural body made of semiconductor material includes an active area housing a drain region, a body region and a source region within the body region. An electrical-isolation trench extends in the structural body to surround the active area. A first PN-junction and a second PN-junction are integrated in the structural body between the active area and the trench, respectively located on opposite sides of the active area. The first and the second PN-junctions form a first diode and a second diode, with each diode having a respective cathode electrically coupled to the drain region of the MOSFET device and a respective anode electrically coupled to the source region of the MOSFET device.

Abstract: A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.

Abstract: An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.

Abstract: A DC-DC converter includes a power oscillator connected to a first transformer winding, and a channel conveying a data stream through galvanic isolation by power signal modulation. A rectifier rectifies the power signal to produce a DC voltage. A comparator produces an error signal from the DC voltage and a reference voltage. An analog-to-digital converter converts the error signal to a digital power control value. A multiplexer multiplexes the digital power control value with the data stream to obtain a multiplexed bitstream. A transmitter driven by the multiplexed bitstream performs amplitude modulation of the power signal at a second transformer winding. A receiver connected to the first winding demodulates the amplitude modulated power signal. A demultiplexer demultiplexes the data stream and the digital power control value. A digital-to-analog converter converts the digital power control value to an analog control signal for the power oscillator.

Abstract: An oscillator circuit including a ring oscillator and a reference current source is provided. The ring oscillator includes an odd number of inverter stages. Each inverter stage includes a first transistor having a first reference threshold that varies over temperature. The reference current source is configured to generate a plurality of currents, where a respective current is applied directly to the drain of a respective first transistor of a respective inverter stage. The reference current source includes a reference transistor that has a second reference threshold that varies over temperature; a resistor coupled between a gate and a source of the reference transistor; a second transistor having a source coupled to the gate of the reference transistor for generating a reference current that flows through the resistor to regulate a voltage of the resistor to the second threshold voltage; and a current mirror configured to generate the plurality of currents.

Abstract: A micro-electro-mechanical device formed in a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region above the first buried cavity; and a second buried cavity extending in the sensitive region. A decoupling trench extends from a first face of the monolithic body as far as the first buried cavity and laterally surrounds the second buried cavity. The decoupling trench separates the sensitive region from a peripheral portion of the monolithic body.

Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

Abstract: A micro-electro-mechanical (MEMS) actuator device includes a frame, and a first functional sub-structure positioned within the frame and mechanically coupled thereto by supporting elements. The first functional sub-structure is subdivided into first and second portions. The first portion is subdivided into first and second sub-portions separated from one another by a first through trench, and the second portion is subdivided into first and second sub-portions separated from one another by a second through trench. First and second piezo-electric structures are respectively carried by the first and second sub-portions of the first portion. Third and fourth piezo-electric structures are respectively carried by the first and second sub-portions of the second portion. A third through trench extends between the frame and the first functional sub-structure except for regions in which the supporting elements are present.

Abstract: A piezoelectric MEMS transducer formed in a body of semiconductor material, which has a central axis and a peripheral area and comprises a plurality of beams, transverse to the central axis and having a first end, coupled to the peripheral area of the body, and a second end, facing the central axis; a membrane, transverse to the central axis and arranged underneath the plurality of beams; and a pillar, parallel to the central axis and rigid with the second end of the beams and to the membrane. The MEMS transducer further comprises a plurality of piezoelectric sensing elements arranged on the plurality of beams.

Abstract: A differential amplifier generates an output voltage waveform exhibiting a slew rate over a rise time. The amplifier is powered from a dc voltage input and includes a set of differential pairs having a bias current flowing therethrough and a Miller compensation capacitance. A comparator functions to compare a voltage at the dc voltage input against a reference voltage in order to detect when the voltage drops below the reference voltage. A gain stage controls the gain of the differential amplifier and a bias current control circuit controls the bias current of the differential amplifier. In response to the detection by the comparator of the voltage dropping below the reference voltage, the gain stage and the bias current control circuit decrease the gain of the amplifier and jointly decrease the bias current in order to maintain a value of the rise time.

Abstract: A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

Abstract: A microelectronic device includes a chip housing a functional part and carrying first electrical contact regions in electrical connection with the functional part through first protected connections extending over or in the chip. A substrate has a first contact area and a second contact area, which is remote from the first contact area. The first contact area carries second electrical contact regions, and the second contact area carries external connection regions. The second contact regions and the external connection regions are in mutual electrical connection through second protected connections extending over or in the substrate. A protection-ring structure surrounds the first and second electrical contact regions and delimits a first chamber closed with respect to the outside. The first electrical contact regions and the second electrical contact regions are in mutual electrical contact.

Abstract: A heart-rate associated with a heartbeat signal is determined. A transform is selected based on the determined heart-rate associated with the heartbeat signal and a reference heart-rate associated with a dictionary of a sparse approximation model. The transform is selected independent of other factors associated with generation of the heartbeat signal. The selected transform is applied to the dictionary of the sparse approximation model, generating an adjusted dictionary of the sparse approximation model. Anomalous heartbeats in the heartbeat signal are detected using the adjusted dictionary of the sparse approximation model.

Abstract: A system to manage out-of-order traffic in an interconnect network has initiators that provide requests through the interconnect network to memory resource targets and provide responses back through the interconnect network. The system includes components upstream the interconnect network to perform response re-ordering, which include memory to store responses from the interconnect network and a memory map controller to store the responses on a set of logical circular buffers. Each logical circular buffer corresponds to an initiator. The memory map controller computes an offset address for each buffer and stores an offset address of a given request received on a request path. The controller computes an absolute write memory address where responses are written in the memory, the response corresponding to the given request based on the given request offset address.

Abstract: A system for detecting objects, for driver assistance equipment in motor vehicles for example, includes a transmitter for transmitting towards an object an optical signal having a signal energy. The optical signal transmitted includes at least one encoded pulse sequence with the signal energy distributed over the pulse sequence. A receiver receives an echo signal resulting from reflection of the optical signal at the object with the time delay of the echo signal is indicative of the distance to the object.

Abstract: A method is for reducing pulse skipping from a characteristic affecting a modulating signal input to an integrator of a pulse width modulation (PWM) modulator, together with a square wave carrier signal for generating a triangular waveform of the PWM modulator. The method may include creating a broad synchronous peak at vertexes of the triangular waveform output by the integrator.

Abstract: A microelectromechanical device includes: a body accommodating a microelectromechanical structure; and a cap bonded to the body and electrically coupled to the microelectromechanical structure through conductive bonding regions. The cap including a selection module, which has first selection terminals coupled to the microelectromechanical structure, second selection terminals, and at least one control terminal, and which can be controlled through the control terminal to couple the second selection terminals to respective first selection terminals according, selectively, to one of a plurality of coupling configurations corresponding to respective operating conditions.