Abstract: A high-to-low voltage interface circuit includes a differential circuit stage with a differential amplifier circuit having inverting and non-inverting inputs coupled to first and second input pads as well as a differential output having first and second output nodes. A pair of bias amplifier stages sensitive to the common mode voltage of the differential amplifier circuit are arranged in first and second current mirror paths from the first and second input pads to the inverting/non-inverting inputs of the differential amplifier circuit, respectively. The bias amplifier stages are configured to maintain the first input pad and the second input pad of the differential circuit stage at the common mode voltage.
Abstract: An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.
Type:
Application
Filed:
February 4, 2020
Publication date:
August 13, 2020
Applicant:
STMicroelectronics S.r.l.
Inventors:
Calogero Marco IPPOLITO, Michele VAIANA, Angelo RECCHIA
Abstract: A microelectromechanical transducer includes: a semiconductor body, having a first surface and a second surface opposite to one another; a first structural body, coupled to the first surface of the semiconductor body; a first sealed cavity between the semiconductor body and the first structural body; and an active area housed in the first sealed cavity, including at least two trenches and a sensor element between the trenches. The trenches extend along a vertical direction from the first surface towards the second surface of the semiconductor body.
Type:
Grant
Filed:
April 25, 2018
Date of Patent:
August 11, 2020
Assignee:
STMICROELECTRONICS S.r.l.
Inventors:
Mohammad Abbasi Gavarti, Daniele Caltabiano, Anna Angela Pomarico, Giuditta Roselli
Abstract: A signal receiver method to achieve satellite position fix by improving satellite orbit prediction includes: acquiring satellite signals and navigation data and calculating a position solution, which includes predicting the state or orbit of one or more satellites. The prediction includes using a model of the solar radiation pressure operating on a selected satellite.
Abstract: A method of sensing a temperature includes providing a voltage to reverse bias a PN junction of a junction diode. The PN junction has a junction capacitance. The method includes providing a reverse bias voltage change across the PN junction and detecting a value of the junction capacitance in response to the reverse bias voltage change. The value of the junction capacitance is a function of a temperature of the PN junction. An output signal is generated based on the detected junction capacitance, where the output signal indicates a temperature of an environment containing the junction diode.
Type:
Grant
Filed:
April 25, 2019
Date of Patent:
August 11, 2020
Assignee:
STMicroelectronics S.r.l.
Inventors:
Michele Vaiana, Daniele Casella, Giuseppe Bruno
Abstract: A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.
Type:
Grant
Filed:
November 19, 2018
Date of Patent:
August 11, 2020
Assignee:
STMICROELECTRONICS S.r.l.
Inventors:
Mauro Mazzola, Battista Vitali, Matteo De Santa
Abstract: A multi-phase electric motor includes a stator winding. The multi-phase electric motor is controlled by regulating a current flowing in the multi-phase electric motor in response to an applied voltage. An overload condition of the multi-phase electric motor is detected by monitoring a thermal increase of the value of a stator resistance of the stator winding of the multi-phase electric motor during a steady state condition of said multi-phase electric motor in which the current flowing in the motor has constant phase, and the motor is operating at constant load with constant speed.
Abstract: An operational amplifier including an input stage coupled to an input terminal, an output stage coupled to an output terminal, and a gain node between the input stage and the output stage. A bias current source is couplable to the input stage to supply a bias current thereto and a current mirror circuit mirrors the bias current toward the gain node and the output stage. A switch circuit includes a switch activatable to bring the gain node to a pre-bias voltage and a switch coupled to the output stage and switchable between a first state and a second state in which the output stage is active and non-active, respectively—. A further switch circuit is coupled to the output terminal and switchable between a first state and a second state in which the output stage is coupled to the output terminal and to a reference level, respectively.
Type:
Grant
Filed:
August 30, 2017
Date of Patent:
August 4, 2020
Assignee:
STMICROELECTRONICS S.r.l.
Inventors:
Andrea Gambero, Davide Ugo Ghisu, Sandro Rossi
Abstract: A circuit for an ultrasonic channel has a first and a second terminal between which extend a resistive and diode signal paths including a pair of diodes with opposing polarities, for example in anti-parallel. Switching circuitry is coupled with the resistive and diode signal paths and is switchable between first and second states. In the first state, the first and the second terminals are coupled with one another via the resistive signal path. In the second state, the first and the second terminals are coupled with one another via the diode signal path. The switching circuitry includes first and second transistor discharge circuits coupled between first and second drive lines and current paths of these transistors, and coupled to control terminals of these transistors. The control terminals are coupled to the first or second drive line and are non-conductive and conductive in first and second operating states, respectively.
Type:
Grant
Filed:
August 30, 2017
Date of Patent:
August 4, 2020
Assignee:
STMICROELECTRONICS S.r.l.
Inventors:
Davide Ugo Ghisu, Sandro Rossi, Andrea Gambero
Abstract: An integrated electronic device forming a power device and including: a semiconductor body; a first conductive region and a second conductive region, which extend over the semiconductor body, the second conductive region surrounding the first conductive region at a distance; and an edge termination structure, which is arranged between the first and second conductive regions and includes a dielectric region, which delimits an active area of the power device, and a semiconductive structure, which extends over the dielectric region and includes a plurality of diode chains, each diode chain including a plurality of first semiconductive regions of a first conductivity type and a plurality of second semiconductive regions of a second conductivity type, the first and second semiconductive regions being arranged in alternating fashion so as to form a series circuit including a plurality of first and second diodes, which are spaced apart from one another and have opposite orientations.
Type:
Grant
Filed:
November 9, 2018
Date of Patent:
August 4, 2020
Assignee:
STMICROELECTRONICS S.r.l.
Inventors:
Fernando Giovanni Menta, Salvatore Pisano
Abstract: A microelectromechanical force/pressure sensor has: a sensor die, of semiconductor material, having a front surface and a bottom surface, extending in a horizontal plane, and made of a compact bulk region having a thickness along a vertical direction, transverse to the horizontal plane; piezoresistive elements, integrated in the bulk region of the sensor die, at the front surface thereof; and a cap die, coupled above the sensor die, covering the piezoresistive elements, having a respective front surface and bottom surface, opposite to each other along the vertical direction, the bottom surface facing the front surface of the sensor die.
Type:
Grant
Filed:
February 12, 2018
Date of Patent:
July 28, 2020
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Mohammad Abbasi Gavarti, Daniele Caltabiano, Andrea Picco, Anna Angela Pomarico, Giuditta Roselli, Francesco Braghin
Abstract: A micro-electro-mechanical device, wherein a platform is formed in a top substrate and is configured to turn through a rotation angle. The platform has a slit and faces a cavity. A plurality of integrated photodetectors is formed in a bottom substrate so as to detect the light through the slit and generate signals correlated to the light through the slit. The area of the slit varies with the rotation angle of the platform and causes diffraction, more or less marked as a function of the angle. The difference between the signals of two photodetectors arranged at different positions with respect to the slit yields the angle.
Abstract: A control unit for a switching converter has an inductor element coupled to an input and a switch element coupled to the inductor element and generates a command signal having a switching period to switch the switch element and determine a first time period in which an inductor current is flowing in the inductor element for storing energy and a second time period in which energy is transferred to a load. An input current is distorted relative to a sinusoid by a distortion factor caused by current ripple on the inductor current. The duration of the first time period is determined based on a comparison between a peak value of the inductor current and a current reference that is a function of an output voltage of said voltage converter. A reference modification stage modifies one of the current reference and sensed value of the inductor current to compensate for distortion introduced by the distortion factor on the input current.
Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.
Type:
Grant
Filed:
July 19, 2019
Date of Patent:
July 28, 2020
Assignees:
STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
Abstract: A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.
Type:
Application
Filed:
January 16, 2020
Publication date:
July 23, 2020
Applicant:
STMicroelectronics S.r.l.
Inventors:
Alberto ARRIGONI, Giovanni GRAZIOSI, Aurora SANNA
Abstract: A first wafer of semiconductor material has a surface. A second wafer of semiconductor material includes a substrate and a structural layer on the substrate. The structural layer integrates a detector device for detecting electromagnetic radiation. The structural layer of the second wafer is coupled to the surface of the first wafer. The substrate of the second wafer is shaped to form a stator, a rotor, and a mobile mass of a micromirror. The stator and the rotor form an assembly for capacitively driving the mobile mass.
Type:
Application
Filed:
January 16, 2020
Publication date:
July 23, 2020
Applicant:
STMicroelectronics S.r.l.
Inventors:
Luca SEGHIZZI, Linda MONTAGNA, Giuseppe VISALLI, Mikel AZPEITIA URQUIA
Abstract: A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node.
Type:
Grant
Filed:
April 4, 2019
Date of Patent:
July 21, 2020
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Francesco Pulvirenti, Salvatore Cassata, Salvatore Giuseppe Privitera
Abstract: A thermoelectric energy harvesting device including a first thermal-coupling interface, a second thermal-coupling interface, and a membrane. The membrane arranged between the first thermal-coupling interface and the second thermal-coupling interface and connected to the first thermal-coupling interface by a supporting frame. A thermal bridge between the second thermal-coupling interface and a thermal-coupling portion of the membrane. A thermoelectric converter on the membrane configured to supply an electrical quantity as a function of a temperature difference between the thermal-coupling portion of the membrane and the supporting frame.
Type:
Grant
Filed:
December 30, 2015
Date of Patent:
July 21, 2020
Assignee:
STMICROELECTRONICS S.r.l.
Inventors:
Giuseppe Antonio Maria Nastasi, Roberta Giuffrida, Agatino Minotti, Giuseppe Catania, Salvatore Leonardi
Abstract: A method includes providing a semiconductor wafer that includes at least one optical waveguide extending in a longitudinal direction. Stealth dicing laser processing is applied to the semiconductor wafer by producing defect regions into the wafer along at least one cutting line. The cutting line is oblique to the longitudinal direction of the at least one optical waveguide. The wafer is expanded to induce fracture thereof at the at least one cutting line, thereby producing an end surface of the at least one optical waveguide. The end surface is oblique to the longitudinal direction of the at least one optical waveguide.
Abstract: A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.
Type:
Grant
Filed:
April 11, 2017
Date of Patent:
July 21, 2020
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Maurizio Francesco Perroni, Giuseppe Castagna