Abstract: A protection method may prevent a load-mismatch-induced failure in solid-state power amplifiers. In an RF power amplifier, the load voltage standing-wave ratio results in very high voltage peaks at the collector of the final stage and may eventually lead to permanent failure of the power transistor due to avalanche breakdown. The method avoids breakdown by attenuating the input power to the final stage during overvoltage conditions, thus limiting the output collector swing. This is accomplished by a feedback control system, which detects the peak voltage at the output collector node and clamps its value to a given threshold by varying the circuit gain. Indeed, the control loop is unlocked in the nominal condition and it acts when an output mismatching condition is detected. A control circuit also allows a supply-independent collector-clamping threshold to be accurately set.

Abstract: A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

Abstract: A method for estimating the white Gaussian noise level that corrupts a digital image by discriminating homogeneous blocks from blocks containing a textured area and skipping these last blocks when evaluating the noise standard deviation.

Abstract: The nonvolatile storage device is made up of a memory array divided into a plurality of data-storage units and a plurality of redundancy-storage units for replacing respective failed data-storage units. A control unit detects the functionality of the data-storage units and, in case of failure, enables a redundancy-detection unit having a plurality of volatile-memory elements connected through a sequential daisy-chain connection. A nonvolatile memory unit stores, in a nonvolatile way, the redundancy information through a data bus, connected both to the redundancy-detection unit and to the nonvolatile memory unit; in the event of failure, the redundancy-detection unit transfers the addresses of the failed data-storage unit to the nonvolatile memory unit for their nonvolatile storage.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.

Abstract: A method and a relative test structure for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. This approach addresses the problem of short-circuit currents that affect known test structures, and allows a direct measurement of the coupling capacitance between the two interconnect lines. Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.

Abstract: A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.

Abstract: A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing the visible index on each die includes: forming in a first material layer of the die a reference structure adapted to defining a mapping of the wafer; and forming in a second material layer of the die a marker associated with the reference structure, a position of the marker with respect to the reference structure being adapted to provide an indication of the die position in the wafer.

Abstract: A digital-to-analog converter includes a first section (MSB) that converts the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (?V1). A second section (LSB) of the converter converts the less significant bits of the digital code into a current. The current is transformed into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (?V2) equal to ½ L of the product of the first voltage step (?V1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted. A summer generates an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summer has a resistive feedback circuit including a voltage divider (R3, R4).

Abstract: A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.

Abstract: A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline read voltage, where one of the steps of first connecting and second connecting is carried out before charging the bitline and the other of the steps of first connecting and second connecting is carried out after charging the bitline. An order of carrying out the steps of first connecting and second connecting is determined based on an address of a selected cell.

Abstract: An electronic system supporting modular expansion of its functions is of a type including a portable host electronic device associated with an expansion module adapted for quick-connect engagement and disengagement in/from the portable device. The expansion module includes a series of peripheral devices adapted to serve different classes of functions; a non-volatile memory storing information that pertains to configuring the different functions in the module; a re-configurable device adapted to establish connections, implement functional portions, and control all the system components; a control device adapted to cooperate with the host device in guiding the steps for re-configuring the whole system; and a software algorithm adapted to instruct the system to re-configure itself on which function and with which characteristics.

Abstract: A method for controlling the bit-rate of a bitstream of encoded video signals at a variable bitrate, the bitstream being generated by compressing a video sequence of moving pictures, wherein each picture comprises a plurality of macroblocks of pixels compressed by any of transform coding, temporal prediction, bi-dimensional motion compensated interpolation or combinations thereof, to produce any of I and/or P and/or B frames, the method involving quantization of said macroblocks effected as a function of a quantization parameter.

Abstract: An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.

Abstract: A manufacturing method for a power device integrated on a semiconductor substrate with double thickness of a gate dielectric layer is described, which comprises the following steps: forming first dielectric portions having a first thickness; forming on the whole semiconductor substrate a first dielectric layer thinner than the first dielectric portions; forming a conductive layer on the first dielectric layer; forming a second dielectric layer on the conductive layer; performing an etching step of the second dielectric layer and of the conductive layer to form first spacers and a gate electrode, to define, between the gate electrode and the substrate, second dielectric portions in the first dielectric layer, the second dielectric portions being auto-aligned with the first portions.

Abstract: A surface acoustic wave pressure sensor includes: a substrate and at least one flexible membrane, suspended over a cavity defined in the thickness of the substrate, the membrane being elastically deformable by a pressure applied by a fluid and being defined between a first surface facing the cavity and a second opposite surface; a SAW device comprising a layer of piezoelectric material arranged on the second surface of the membrane, the SAW device further comprising at least one SAW electro-acoustic transducer formed on one free surface of the piezoelectric layer. The piezoelectric layer is formed by deposition of piezoelectric material on the membrane and the substrate is integrated in a chip of semiconductor material, the membrane being a layer of the chip suspended over the cavity.

Abstract: A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.

Abstract: A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.

Abstract: The evaluation time or the difference between the read charge voltage and the read discrimination voltage of the programmed or erased state of a cell of a NAND memory array is set for the individual memory device. This is done in such a way that at least partially compensates the generally large spread of parasitic capacitance values of the array bitlines in the mass production fabrication process of the NAND memory array.

Abstract: A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.