Abstract: A clock and data recovery method comprising the following steps: an oversampling step wherein an oversampled stream of samples is generated from an input data stream at a data rate by using reference clock signal at a clock rate, the clock rate being higher than the data rate, and a tracking step of the input data stream realised by locating transitions between adjacent samples of the oversampled stream and by moving a no transition area within the oversampled stream wherein no transitions between adjacent samples are found a recovered data signal being obtained as a central portion of the no transition area and a recovered clock signal being obtained by dividing the reference clock signal. A clock and data recovery device is also described.

Abstract: A scan compression architecture for a design for testability compiler used in system-on-chip software design tools includes a first scan architecture including a first scan compressor/decompressor configuration connected to a first predetermined set of pins, and a second scan architecture including a second scan compressor/decompressor configuration connected to a subset of the pins. The first scan architecture is selectively enabled for executing a scan test with a low time. The second scan architecture is for executing a scan test with high parallelism.

Abstract: A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.

Abstract: A fast method of color interpolation of pixels of an image acquired by a color filtered digital sensor uses a very simple cost function that nevertheless produce interpolated images of good quality. The cost function is computationally simpler because it does not require the calculation of powers and square roots. The triangulation algorithm may be executed in far less time, while practically ensuring the same performance. The triangulation algorithm on average may use only two iteration steps. The interpolation process may be followed by an anti-aliasing processing that effectively removes color artifacts.

Abstract: Subdivision per basic color channels of grey level data generated by a color sensor is no longer required according to a novel color interpolation method of an image acquired by a digital color sensor generating grey levels for each image pixel as a function of the filter applied to the sensor by interpolating the values of missing colors of each image pixel for generating triplets or pairs of values of primary colors or complementary base hues for each image pixel. The method may include calculating spatial variation gradients of primary colors or complementary base hues for each image pixel and storing the information of directional variation of primary color or complementary base hue in look-up tables pertaining to each pixel.

Abstract: A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers. The test chip includes a ROM memory array. The vias to be measured are formed in the columns of the array. Via or contact failures are detected by forcing a predetermined current through both an array column and a reference column. The failure analysis is obtained by comparing the resulting voltage drops.

Abstract: The method controls a charge pump generator having at least an output tank capacitor on which a regulated output voltage of the generator is produced, and a pump capacitor that is connected to a supply node and to ground during charge phases and is coupled in an anti-parallel configuration to the output tank capacitor during charge transfer phases, alternated to the charge phases. The method limits the current absorbed from the supply because the transfer capacitor is charged during at least an initial charge phase with a constant charge current of a pre-established value.

Abstract: A method for simultaneously programming a pre-established number of memory cells includes setting an initial number of memory cells to be simultaneously programmed equal to the pre-established number, and subdividing the initial number of memory cells to be programmed into subsets of memory cells. A program operation for simultaneously programming all the memory cells of each subset of memory cells is executed by forcing a current through all the memory cells of each subset of memory cells. The current has a program voltage associated therewith. The program voltage is compared to a threshold voltage during execution of the program operation. The method further includes stopping execution of the program operation if the threshold voltage is surpassed, reducing the initial number of memory cells to be simultaneously programmed, and restarting from the subdividing.

Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract: The output buffer stage includes a half-bridge output stage having a first pair of complementary drivers connected in series between a supply line and a ground node, the high impedance state or conduction state of which is determined through a pair of control phases. The buffer stage includes a pair of switches controlled by the control phases, connected in series between them and connecting the transistors of the first stage in series. Each driver is connected in series with a switch, that is quickly opened to prevent under-threshold currents from circulating when the respective driver is turned off, and that is rapidly turned off when the respective driver is turned on.

Abstract: Precision and reliability of a current limited mode output power control of an RF amplifier is enhanced by sensing the base current of the current controlled output power transistor. The base current is compared to a control current that is normalized by scaling it as a function of the current gain of a bipolar junction transistor of similar characteristics as the output power transistor. Fabrication process spread of current gain figures of bipolar junction transistors is effectively compensated. Moreover, by using a band-gap temperature compensation control current that is eventually ?-scaled before comparing it with the sensed base current of the output power transistor, the output power may be effectively controlled and maintained constant over temperature as well as process spread variations.

Abstract: A driving circuit of a switch includes first and second transistors connected in series to each other and to relative intrinsic diodes in antiseries and driven by a driving device that includes at least one first and one second output terminal connected to the switch to supply it with a first control signal for driving the switch in a first working state and a second control signal for driving the switch in a second working state. At least one latch circuit coupled between respective common gate and source terminals of the first and second transistors supplies the common gate terminal with the first and second control signals, respectively, according to the working state to turn off and turn on the first and second transistors.

Abstract: Digital signals are converted between a first and second format by a conversion process including generating coefficients representing the digital signals. The coefficients may be discrete cosine transform coefficient generated during encoding/transcoding of MPEG signals. The coefficients are subject to quantization by generating a dither signal that is added to the coefficients before quantization to generate a quantized signal. Preferably, each coefficient is first subject to a first quantization in the absence of any dither signal added to generate an undithered quantized coefficient. If the undithered quantized signal is equal to zero the undithered quantized coefficient is taken as the output quantized signal. If the undithered quantized coefficient is different from zero, the dither signal is added and the dithered coefficient thus obtained is subject to quantization to generate the output quantized signal.

Abstract: A reliable method of sensing the inlet air flow in a combustion chamber of a cylinder of an internal combustion engine includes assessing the inlet air flow with soft-computing techniques basically exploiting a combustion pressure signal generated by a pressure sensor installed in the cylinder.

Abstract: A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The register includes multiple latches and multiple buffer elements. Each of the latches is coupled to at least one signal line for transferring the data bit that is stored in the latch. Each of the buffer elements decouples an output of a corresponding one of the latches from the signal line, with the buffer element driving the signal line according to the data bit stored in the corresponding latch. Also provided is a method of transferring data from a register to signal lines in an electrically programmable memory.

Abstract: A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.

Abstract: A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix divided into sectors being singularly erasable and organized in rows or word lines and columns or bit lines of memory cells. Advantageously, the matrix may include logic sectors wherein pairs of rows or word lines are electrically short-circuited and refer to a single biasing terminal, source terminals of the associated cells of each pair of rows associated with a same source select line referring to a corresponding biasing terminal, and at least one pair of independent drain select lines, each of the rows and of the lines being provided with metallization shunts to by-pass groups of bit lines and/or to speed up the propagation times of the biasing in the corresponding logic sector.

Abstract: To obtain frame synchronization and identify the cell codegroup in a cellular communication system (such as a system based upon the standard 3GPP FDD), there are available the synchronization codes organized in chips or letters transmitted at the beginning of respective slots. Slot synchronization is obtained previously in a first step of the operation of cell search. During a second step, there are acquired, by means of correlation or fast Hadamard transform, the energy values corresponding to the respective individual letters with reference to the possible starting positions of the corresponding frame within the respective slot. Operating in a serial way at the end of acquisition of the aforesaid energy values of the individual letters, or else operating in parallel, the energies of the corresponding words are determined. Of these energies only the maximum word-energy value and the information for the corresponding starting position are stored in a memory structure.

Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.

Abstract: The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.