Abstract: A voltage regulator integrated in a chip of semiconductor material is provided.

Abstract: A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines. The managing logic includes a control block for generating a first enable signal of the precharge step and a second enable signal of the turning on step such that, within the same reading operation, the precharge and turning on steps are partially concurrent.

Abstract: An automatic redundancy system may exploit an existing microprocessor management system on chip for carrying out autonomously, without communicating with an external testing machine, the operations of: writing data in the memory array according to one or more pre-established test patterns, verifying data successively read from the memory array, and substituting failed elements of the memory array with equivalent redundancy structures. A logic structure may detect and store memory array failures upstream of the output data path. Thereby, data collection relating to failures may be accomplished more quickly and without any interaction with the testing machine apart from communicating the end of the execution of the redundancy process.

Abstract: A solid-state mass storage device is provided. The solid-state mass storage device defines a storage area adapted to store data; the storage area is adapted to be exploited for storing data with a first storage density at a first data transfer speed. The storage area includes at least a first storage area portion and a second storage area portion. The solid-state mass storage device further includes accessing logic adapted to exploit the first storage area portion for storing data with a second storage density at a second data transfer speed, and adapted to exploit the second storage area portion for storing data with a third storage density and a third data transfer speed. The second storage density is lower than the third storage density, which is in turn lower than or equal to the first storage density; the second data transfer speed is higher than the third data transfer speed, which is in turn higher than or equal to the first data transfer speed.

Abstract: An address counter for a nonvolatile memory device includes a cascade of cells. Each cell includes an address counting flip-flop that is updated to a value of every newly counted address bit, or latches a column address bit value input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page. Each cell further includes an additional address loading flip-flop for loading the column address bit value input during ALE cycles for addressing the start memory location on the selected page during the ALE cycles. A logic circuit updates the address counting flip flop to the address bit value during a read confirm cycle in a read sequence, and during a first data input cycle in a program sequence.

Abstract: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract: A power on reset circuit initializes at power on a digital integrated circuit, and includes a first power on reset signal generator powered by an external power supply voltage and generates a first power on reset signal. A reference voltage generator is powered by the external power supply voltage, and is enabled by the first power on reset signal for generating a stable compensating reference voltage. A voltage down converter circuit receives the reference voltage and is enabled by the first power on reset signal, and converts the external applied power supply voltage to a stable regulated internal supply voltage. A second power on reset signal generator circuit receives the regulated internal supply voltage, and is enabled by the first power on reset signal for generating a second power on reset signal for core parts of the digital integrated circuit for initializing them at power on.

Abstract: A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell.

Abstract: A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.

Abstract: A method is provided for using SACVD deposition to deposit at least one layer of dielectric material inside a deposition reactor during the fabrication of at least one semiconductor integrated circuit. According to the method, a reaction chamber is provided for carrying out SACVD deposition, and a stream of a first reaction gas containing oxygen plasma is supplied into a gas feed conduit connected to the reaction chamber. Microwaves are applied inside the gas feed conduit in order to produce sufficient oxygen radicals from the oxygen plasma, the oxygen radicals being necessary to initiate SACVD deposition. A stream of a second reaction gas is supplied into the reaction chamber, with the second reaction gas being suitable to initiate SACVD deposition when reacting with oxygen radicals.

Abstract: An oscillator system may include an oscillator block having a plurality of inputs and outputting a clock signal, a frequency divider block receiving the clock signal and outputting a divided clock signal, a tuning block receiving the divided clock signal and outputting a comparison signal, and a control block coupled to the tuning block. The control block may receive the comparison signal. The control block may include a configuration block for producing a plurality of outputs for the corresponding inputs of the oscillator block, and an Up/Down counter having outputs applied to the configuration block.

Abstract: A low noise amplifier is provided that includes a first circuit block capable of amplifying a first voltage signal that is input to the amplifier. The first circuit block includes a first terminal coupled to a first supply voltage by a variable resistance, and a second terminal coupled to a second supply voltage. The second terminal is coupled to an output terminal of the amplifier, and the first voltage signal is applied to a further terminal of the first circuit block. The amplifier also includes a feedback network coupled to the output terminal and to the further terminal of the first circuit block, and a second circuit block coupled between the second supply voltage and the further terminal of the first circuit block. The second circuit block is adapted to compensate for variations in value of the variable resistance to ensure a substantially constant input resistance of the amplifier.

Abstract: An integrated control and power driving system moves a read/write head carrying arm over the surface of a disk. The integrated control and power driving system is applicable to a spindle motor, a mass storage disk drive and a voice-coil motor, for example, and includes a first chip and a second chip. The first chip integrates the output power stages driving the motors, and has an interface for outputting feedback signals representing functioning conditions of the voice-coil motor and of the spindle motor, and for receiving digital control signals of the output power stages. The second chip integrates logic drive and control circuitries of the power stages and an interface for receiving the feedback signals output by the first chip, and for transmitting to the first chip the digital control signals.

Abstract: A quantum gate for running a Grover's quantum algorithm using a binary function having a vector basis of n qubits is provided. The quantum gate includes a superposition subsystem, an entanglement subsystem and an interference subsystem. The interference subsystem performs an interference operation on components of entanglement vectors for generating components of output vectors. The interference subsystem performs the interference operation in a very fast manner by using an adder receiving as input signals representing even or odd components of an entanglement vector, and generating a sum signal representing a weighted sum with a scale factor of the even or odd components.

Abstract: A method for controlling a PWM power stage is based upon dampening current peaks generated by switching of the PWM power stage. The PWM power stage includes at least two MOS transistors of opposite conductivity coupled between an output node of the PWM power stage and respective positive and negative supply lines, and respective free-wheeling diodes. The method includes forming the at least two MOS transistors such that their reverse conduction threshold voltage is smaller than a sum between their forward conduction threshold voltage and a forward voltage on the respective free-wheeling diode at which a pre-established current flows therethrough. The at least two MOS transistors are in a high impedance state by biasing respective control nodes at a turn-off voltage such that their gate-source voltage is between the forward conduction threshold voltage and a null voltage.

Abstract: To execute the cell-search procedure in a cellular communication system (such as a system based upon the 3GPP TDD standard), there are available identification codes for the second step (slot synchronization) and for the third step (identification of the scrambling codes). The identification codes are identified by a process of correlation with the received signal and are used for obtaining from a correspondence table the parameters for the execution of the second step (CD) or of the third step (SCR). The correspondence table is stored in a reduced form by the identification, according to rules of symmetry and redundancy, of subtables designed to generate the entire table by appropriate combination operations. The search procedure in the correspondence table thus reduced is conveniently modified by the introduction of the combination operations. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

Abstract: A method for extracting a subset of data from an ordered set of bi-dimensional matrices (data arrays) such as a sequence of pictures or a multi-dimensional matrix, for instance, is implemented by dedicated hardware that may be used each time it is necessary to extract a subset of data from a data array. For each matrix of data, the method calculates very quickly row and column indices of border data of the portion to be extracted, which are obtained by arithmetical operations among row and column indices of vertices of a closed area of interest. The method is implemented in a device for selectively transferring a data stream sampled at a certain bit-rate to a microprocessor unit or to a memory receiving the data stream at a different rate.

Abstract: An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.

Abstract: In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Abstract: The present invention relates to a new light emitters that exploit the use of semiconducting single walled carbon nanotubes (SWNTs). Experimental evidences are given on how it is possible, within the standard silicon technology, to devise light emitting diodes (LEDs) emitting in the infrared IR where light emission results from a radiative recombination of electron and holes on semiconducting single walled carbon nanotubes (SWNTs-LED). We will also show how it is possible to implement these SWNTs-LED in order to build up a laser source based on the emission properties of SWNTs. A description of the manufacturing process of such devices is also given.