Abstract: A method of feedback controls a switched regulator generating a regulated voltage on an output terminal and being driven by a pulse width modulated (PWM) signal that determines on-phases during which the output terminal is selectively connected to a supply line, and off-phases during which the output terminal is disconnected according to a pulse skipping mode. The method may include comparing the regulated voltage with a reference voltage, and during the on-phase of the PWM signal, selectively connecting or disconnecting the supply line to the output terminal based upon the comparing for keeping the regulated voltage constant. The method may also include incrementing, decrementing, or leaving unchanged a duty-cycle of the PWM signal at every PWM cycle also based upon the comparing.

Abstract: A signal-processing circuit has a first and a second input, which receive a first and a second differential signal, a third input, which receives a common-mode signal, the first and second differential signals having an equal and substantially opposite trend with respect to the common-mode signal, and a first output supplying a first processed signal, equivalent to the first differential signal rectified with respect to the common-mode signal, and satisfying throughout its course a first relation of comparison with the common-mode signal. The processing circuit is provided with first formation means for formation of the first processed signal, which operate on the basis of the first differential signal, and second formation means for formation of the first processed signal, which operate on the basis of the second differential signal; the first and second formation means co-operate in the formation of the first processed signal.

Abstract: Both a chalcogenide select device (24, 120) and a chalcogenide memory element (40, 130) are formed within vias within dielectrics (18, 22). As a result, the chalcogenides is effectively trapped within the vias and no glue or adhesion layer is needed. Moreover, delamination problems are avoided. A lance material (30) is formed within the same via (31) with the memory element (40, 130). In one embodiment, the lance material is made thinner by virtue of the presence of a sidewall spacer (28); in another embodiment no sidewall spacer is utilized. A relatively small area of contact between the chalcogenide (40) used to form a memory element (130) and the lance material (30) is achieved by providing a pin hole opening in a dielectric (34), which separates the chalcogenide and the lance material.

Abstract: A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the dielectric layer until upper portions of the gates of the cells and the conductive layer are exposed, defining a plurality of gate electrodes of the transistors of the circuitry in the conductive layer, and forming source and drain regions of the transistors of the circuitry in the substrate. The method also comprises: forming spacers on side walls of gate electrodes of the transistors of the circuitry, and forming a silicide layer on the electrodes of the cells, on the gate electrodes of the transistors of the circuitry and on the source and drain regions of the transistors of said circuitry.

Abstract: The described integrated planar optical structure comprises a principal waveguide having a core and a cladding that define a first light path ad means sensitive to the light radiated into the cladding comprising at least one secondary waveguide having a core and a cladding that define a second light path. The secondary waveguide has an entry situated in the cladding of the principal waveguide at such a distance from the core of the latter as not to interfere with the propagation of the light along the first optical path and a core section that becomes greater in a first part from the entry onwards to collect the light energy radiated into the cladding. Also described are a system for monitoring the light energy emitted by a source and an optical attenuator that comprise the aforesaid optical structure.

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract: A manufacturing process of a semiconductor piezoresistive accelerometer includes the steps of: providing a wafer of semiconductor material; providing a membrane in the wafer over a cavity; rigidly coupling an inertial mass to the membrane; and providing, in the wafer, piezoresistive transduction elements, that are sensitive to strains of the membrane and generate corresponding electrical signals. The step of coupling is carried out by forming the inertial mass on top of a surface of the membrane opposite to the cavity. The accelerometer is advantageously used in a device for monitoring the pressure of a tire of a vehicle.

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract: In a micro-electromechanical structure, a rotor has a centroidal axis and includes a suspended structure which carries mobile electrodes. A stator carries fixed electrodes facing the mobile electrodes. The suspended structure is connected to a rotor-anchoring region via elastic elements. The stator includes at least one stator element, which carries a plurality of fixed electrodes and is fixed to a stator-anchoring region. One of the rotor-anchoring regions and stator-anchoring regions extends along the centroidal axis and at least another of the rotor-anchoring regions and stator-anchoring regions extends in the proximity of the centroidal axis.

Abstract: A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.

Abstract: A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp.

Abstract: A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.

Abstract: A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.

Abstract: A semiconductor-integrated electronic device comprises a body and a plurality of leads, adjacent and in spaced relationship to each other, projecting from at least one edge of the body. The device further comprises a spacer device which comprises a plurality of insulating teeth interposed between the plurality of leads, so as to form an insulating barrier between adjacent leads of the plurality of leads.

Abstract: A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.

Abstract: A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with a bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) function. A load unit loads into the processor clusters data to be processed according to a same instruction. An intercluster data path exchanges data between the processor clusters. The intercluster data path is scalable to activate selected processor clusters. The processor operates simultaneously on SIMD, scalar and vectorial data.

Abstract: Described herein is an assembly of an integrated device and of a cap coupled to the integrated device; the integrated device is provided with at least a first and a second region to be fluidically accessed from outside, and the cap has an outer portion provided with at least a first and a second inlet port in fluid communication with the first and second regions. In particular, the first and second regions are arranged on a first outer face, or on respective adjacent outer faces, of the integrated device, and an interface structure is set between the integrated device and the outer portion of the cap, and is provided with a channel arrangement for routing the first and second regions towards the first and second inlets.

Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

Abstract: An electro-static discharge protection circuit including: a first input terminal and a second input terminal; a first output terminal coupled to the first input terminal, and a second output terminal coupled to the second input terminal; a first circuit branch connected between the first input terminal and the second input terminal, said first circuit branch including at least one first Zener diode having a cathode terminal and an anode terminal; a second circuit branch connected between the first output terminal and the second output terminal, wherein the first circuit branch comprises a load element coupled between the second input terminal and the anode terminal of the at least one first Zener diode; the second circuit branch includes a first transistor having a control terminal adapted to receive a transistor control voltage, the first transistor being coupled to the load element so as to receive from the load element the transistor control voltage.

Abstract: An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connected to the cells. Each memory cell includes at least one floating gate transistor having a floating gate region projecting from the substrate, and a control gate region capacitively coupled to the floating gate region. Between the cells of opposite word lines, a lateral coating is provided that includes at least one conductive layer floating along the direction of the bit lines.