Abstract: On a semiconductor material body housing an electronic device a peripheral region of semiconductor material and at least one pad are initially formed. The peripheral region is connected to a first terminal of the electronic device and extends on at least one peripheral portion of the semiconductor material body. The pad is insulated from the semiconductor material body and is electrically connected to a second terminal of the electronic device. The semiconductor material body is fixed to a support body formed by a blank belonging to a reel. The pad is connected by a wire to an electrode formed by the blank. Next, a connection region is formed on the peripheral region and surrounds, at least partially, the semiconductor material body and the support body. The connection region is advantageously obtained by galvanic growth.

Abstract: A high-efficiency electronic circuit generates and regulates a supply voltage and includes a charge-pump voltage multiplier which is associated with an oscillator and has an output connected to a voltage regulator in order to ultimately output said supply voltage. Advantageously, the circuit comprises a first hysteresis comparator having as inputs the regulator output and the multiplier output, and comprises a second hysteresis comparator having as inputs a reference potential and a partition of the voltage presented on the regulator output. The comparators are structurally and functionally independent of each other, and their outputs are coupled to the oscillator through a logic circuit to modulate the oscillator operation.

Abstract: A charge pump voltage booster circuit for generating, from a first voltage supplied at the input to the circuit, an output voltage with an absolute value that is higher than the first voltage, comprises at least one stage having a charge pass element and a charge storage capacitor with a first plate connected to an output of the charge pass element and a second plate controlled by a square-wave control signal of period varying between a reference voltage and the first voltage, supplied to the second plate of the capacitor by means of a driver circuit comprising a pull-up transistor and a pull-down transistor connected in series between the first voltage and the reference voltage. Means of overdriving at least one of the said transistors, either the pull-up transistor or the pull-down transistor, supply to the said at least one transistor a firing control voltage that has a higher absolute value than the first voltage.

Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between the two body regions. The first semiconductor region is placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer.

Abstract: A decoding method for a Huffman code includes receiving a continuous stream of coded data each including a variable number of bits at least equal to a minimum number, and obtaining from each item of coded data a corresponding item of source data. The method includes providing a decoding memory structure comprising, for each value of an initial group of bits including a number not greater than the minimum number and for each value of each further bit, a record formed by a flag having an end-of-decoding value or a not end-of-decoding value and a field indicating the source data or the records associated with the values of an immediately following bit depending on whether the flag has, respectively, the end value or the not end value. The record corresponding to the value of the initial group is accessed.

Abstract: The load pump booster device with transfer and recovery of the charge including a charge pump circuit with an output terminal connected to a load capacitor by means of a load node. In turn, the charge pump circuit includes a plurality of transfer transistors connected to one another in series, and define a plurality of transfer nodes. Each transfer node is connected to a storage capacitor. The booster device also includes a plurality of controlled switches interposed between the load node and a respective transfer node, in order to connect to the load node a single one of the transfer nodes. By this means, between the load capacitor and the storage capacitors there takes place a phase of transfer of charge followed by a phase of recovery of charge, from the storage capacitors to the load capacitor. FIG. 1.

Abstract: A microactuator comprises a stator element and a rotor element which are capacitively coupled. The rotor element comprises a suspended mass and a plurality of movable drive arms extending radially from the suspended mass and biased at a reference potential. The stator element comprises a plurality of first and second fixed drive arms associated with respective movable drive arms and biased at a first drive potential. A mechanical damping structure is formed by at least one movable damping arm extending radially from the suspended mass and by at least one first and one second fixed damping arm associated with the movable damping arm and biased at said reference potential, to dampen settling oscillations of the rotor element.

Abstract: A process for manufacturing a resistive structure that has a polysilicon strip laid above a semiconductor substrate is presented. The process begins by using a mask to cover the polysilicon strip. Then, several apertures are made in the mask until portions of the semiconductor strip are uncovered. Next, a dopant is implanted in the polysilicon semiconductor strip through the apertures. Finally, the resistive structure is subjected to a thermal process for diffusing the dopant in such a way to obtain a variable concentration profile in the semiconductor strip.

Abstract: A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon t

Abstract: An interconnect system includes an arbitration unit for arbitration among a plurality of sources or initiators requesting access to resources or targets. The arbitration unit selectively grants the initiators access to the targets as a function of respective priorities. The system includes a programmable control unit for programmably choosing the priorities in question out of group of at least two different priority schemes including a positional fixed priority, programmed fixed priority, and a variable priority based on a respective threshold latency values associated to the initiators.

Abstract: A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell.

Abstract: A reading circuit having an array branch connected to a multi-level array memory cell; a reference branch connected to a reference memory cell; a current/voltage converter stage formed of a current mirror having a variable mirror ratio, connected to the array and reference branches, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated respectively to the currents flowing in the array branch and in the reference branch; and a comparator stage having a first and a second input connected to the array and reference nodes for comparing with one another the array and reference potentials.

Abstract: A memory device comprises a plurality of independent memory sectors, external address signal inputs for receiving external address signals that address individual memory locations of the memory device, the external address signals including external memory sector address signals allowing for individually addressing each memory sector, and a memory sector selection circuit for selecting one of the plurality of memory sectors according to a value of the external memory sector address signals. A first and a second alternative internal memory sector address signal paths are provided for supplying the external memory sector address signals to the memory sector selection circuit, the first path providing no logic inversion and the second path providing logic inversion.

Abstract: A varactor has a gate region, first and second biasing regions of N+ type embedded in a well, and first and second extraction regions of P+ type, forming a pair of PN junctions with the well. The PN junctions are inversely biased and extract charge accumulating in the well, below the gate region, when the gate region is biased to a lower voltage than a predetermined threshold value.

Abstract: An electronic component, such as an IGBT, that presents a control terminal for receiving a stepwise control signal and at least one other terminal adapted for reaching a given voltage level by effect of the application of the step signal, with the possibility of overshoot occurring; and a damping resistive element interposed between the control terminal and the at least one other terminal. The damping resistive element shows a current saturated behavior correlated to voltage increase applied at the terminals towards the given voltage level, thus eliminating the risk of occurrence of overshoot in the voltage of the IGBT collector, and preventing the undesired re-ignition of the IGBT when it is in a cut-off condition, by inducing an overvoltage on the collector terminal. FIG. 5 is the one selected.

Abstract: The method is intended for manufacturing a microintegrated structure, typically a microactuator for a hard-disk drive unit and includes the steps of: forming interconnection regions in a substrate of semiconductor material; forming a monocrystalline epitaxial region; forming lower sinker regions in the monocrystalline epitaxial region and in direct contact with the interconnection regions; forming insulating material regions on a structure portion of the monocrystalline epitaxial region; growing a pseudo-epitaxial region formed by a polycrystalline portion above the structure portion of the monocrystalline epitaxial region and elsewhere a monocrystalline portion; and forming upper sinker regions in the polycrystalline portion of the pseudo-epitaxial region and in direct contact with the lower sinker regions. In this way no PN junctions are present inside the polycrystalline portion of the pseudo-epitaxial region and the structure has a high breakdown voltage.

Abstract: The invention relates to a control circuit for a hysteretic switching voltage regulator, which comprises a logic circuit driving an output stage; a hysteresis comparator comparing the voltage value at the output of the regulator with a reference voltage; a current sensor for sensing, through a comparator, the current drain of a load connected to the output of the regulator. This control circuit further comprises a device for adjusting the hysteresis range of the hysteresis comparator, and a hysteresis frequency sensing and controlling logic portion connected to the output of the hysteresis comparator, the logic portion acting on the frequency adjusting device.

Abstract: A chip of semiconductor material is fixed to a supporting area of a film of insulating material. Electrical interconnecting elements join metallized areas of the chip to the ends of metal strips which form the terminals of the device. To obtain devices with numerous terminals without approaching the dimensional limits imposed by the manufacture of the terminal frames, the interconnecting elements include electrically conductive tracks formed on the film of insulating material. The electrical connection between the ends of the terminals and the tracks is made by strips of anisotropic conductive material.

Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

Abstract: The method is based on the use of an etching mask comprising silicon carbide or titanium nitride for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a masking layer comprising silicon carbide or titanium nitride; defining photolithographically the masking layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.