Abstract: A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

Abstract: A semiconductor memory device having at least one memory cell row, each memory cell having an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to the gate oxide region and electrically insulated by an intermediate dielectric layer interposed therebetween. The gate oxide regions of the select transistors of the at least one row are separated by field oxide regions, and the lower and upper polysilicon layers and the intermediate dielectric layer extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row there is at least one opening in the upper polysilicon layer, intermediate dielectric layer and lower polysilicon layer, inside of which a first contact element suitable to electrically connect the lower and upper polysilicon layers is inserted.

Abstract: The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.

Abstract: A system and method regulates an alternator and includes a circuit for digitally generating a sawtooth waveform. An error amplifier circuit generates a divided down and error amplified alternator system voltage. A comparator circuit receives and compares to each other the digitally generated sawtooth waveform and the error amplified alternator system voltage and has an output to produce an alternator field input signal used for driving the field of an alternator.

Abstract: A method of voltage driving a load using a controlled current includes providing a negative feedback of an output current, measuring the output current on a collector of an output transistor of an output stage, comparing the measured output current with an input current to define a current difference, and providing the current difference at a base of the output transistor to provide the voltage driving.

Abstract: A process for forming a vertical double-diffused metal oxide semiconductor (VDMOS) structure comprising a semiconductor substrate, an epitaxial layer on the substrate, and a dielectric gate layer on the epitaxial layer includes implanting a first concentration dopant of a first conductivity type through an aperture defined by edges of a patterned gate conductor layer on the dielectric gate layer so that the first concentration dopant diffuses to form a body region of the VDMOS structure. A mask is formed on the patterned gate conductor layer and on a first portion of the body region for defining apertures exposing second portions of the body region.

Abstract: Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference.

Abstract: A programming method comprises the steps of applying a ramp voltage having a first slope to the gate terminal of a selected memory cell to rapidly bring the threshold voltage of the selected cell to an intermediate value; then applying a ramp voltage having a second slope lower than the first, to end programming to the desired final threshold value with high precision. Thereby, when a high threshold value is to be programmed, programming time is reduced; on the other hand, if a low threshold value is to be programmed, the slower ramp voltage is applied right from the start, to prevent possible overprogramming of the cell.

Abstract: The method is for controlling a voice coil motor which drives a mechanical arm via a control circuit which sets the output nodes, to which the motor is connected, in a high impedance state for a certain time interval. The method and circuit detect the back electromotive force induced on the motor winding during the time interval, and deliver current pulses for driving the motor. The circuit compares the detected back electromotive force with a certain target value and regulates the amplitude of the driving current pulses as a function of the difference between the detected value of the back electromotive force and a voltage signal representing the desired speed of the arm, according to a pre-established function. A preferred embodiment includes such a function being a pre-established saturated linear characteristic with an offset value.

Abstract: A process for assembling a microactuator on a R/W transducer that includes forming a first wafer of semiconductor material having a plurality of microactuators including suspended regions and fixed regions separated from each other by first trenches; forming a second wafer of semiconductor material comprising blocking regions connecting mobile and fixed intermediate regions separated from each other by second trenches; bonding the two wafers so as to form a composite wafer wherein the suspended regions of the first wafer are connected to the mobile intermediate regions of the second wafer, and the fixed regions of the first wafer are connected to the fixed intermediate regions of the second wafer; cutting the composite wafer into a plurality of units; fixing the mobile intermediate region of each unit to a respective R/W transducer; and removing the blocking regions. The blocking regions are made of silicon oxide, and the intermediate regions are made of polycrystalline silicon.

Abstract: A new memory controller for use in a display, such as a liquid crystal display of the type comprising a set of first drivers, a set of second drivers, a portion of which can be converted to the first drivers, and a RAM memory structured to accept data at an input and output the data to the sets of first and second drivers when a master clock signal is received at the RAM memory. The memory controller includes a clock signal generator structured to generate the master clock signal; and a control signal generator circuit structured to generate control signals for the RAM memory and the sets of first and second drivers.

Abstract: An integrated cellular network structure that is programmable to solve partial derivative differential equations in order to control a phenomenon of diffusion or a propagation of electric drive pulses for robot actuators. Such structure includes analog and digital portions interconnected with each other; the analog portion having a matrix array of analog cells arranged to receive data from an I/O interface, and the digital portion having first and second memory arrays for storing a desired configuration and the initial state of such analog matrix array, respectively.

Abstract: The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.

Abstract: A field effect transistor having a variable doping profile is presented. The field effect transistor is integrated on a semiconductor substrate with a respective active area of the substrate including a source and drain region. A channel region is interposed between the source and drain regions and has a predefined nominal width. The effective width of the channel region is defined by a variable doping profile.

Abstract: A processor is provided with a set of instructions formed in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract: An integrated circuit voltage ramp generator is presented. The circuit includes at least one operational amplifier having a non-inverting input terminal connected to a voltage reference, and having an output terminal coupled in a feedback relationship to an output terminal of the generator circuit. The ramp voltage generator further includes a first storage capacitance connected between the non-inverting input terminal of the operational amplifier and a ground reference, which is loaded by means of a second pumping capacitance connected in parallel to the first capacitance. The pumping and voltage generation is and controlled by a series of passgates coupled to clock signals.

Abstract: An angular speed sensor comprises a pair of mobile masses which are formed in an epitaxial layer and are anchored to one another and to the remainder of the device by anchorage elements. The mobile masses are symmetrical with one another, and have first mobile excitation electrodes which are intercalated with respective first fixed excitation electrodes and second mobile detection electrodes which are intercalated with second fixed detection electrodes. The first mobile and fixed excitation electrodes extend in a first direction and the second mobile and fixed detection electrodes extend in a second direction which is perpendicular to the first direction and is disposed on a single plane parallel to the surface of the device.

Abstract: The invention relates to a ground-compatible inhibit circuit structure and method, for circuits integrated in a semiconductor substrate which is unrelated to ground potential. The circuit structure is integrated in the same substrate as an associated circuit to be inhibited, and the substrate is covered with an epitaxial layer accommodating the components of the inhibit circuit structure. It includes a stable internal voltage reference and a circuit portion for comparing this reference with an inhibit signal in order to block the associated circuit upon a predetermined threshold value being exceeded, even in a condition of the signal potential being higher than the supply potential to the circuit. Advantageously, the epitaxial layer of each well is always at a potential higher than or equal to that of the substrate.

Abstract: The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in a same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading, in a same clock cycle, the stored data word.

Abstract: An improved leadframe for packages of integrated power devices which, by virtue of its configuration, allows to press the dissipator on the bottom of the shell during the molding of the plastic case, without the dissipator having exposed portions of its inner face (which is in contact with the chip). In order to achieve this, the leadframe according to the invention comprises a monolithic body which defines a perimetric frame, the leads and the dissipator. The dissipator extends in a depressed plane with respect to the frame and is connected to the frame and to the leads in at least three step-like points which are mutually spaced and non-aligned. During the molding of the plastic case, a pressure is exerted on the frame and is transmitted to the dissipator by the three step-like points, so that the dissipator is effectively pressed flat against the bottom of the mold without using pushers which pass through the plastic case.