Abstract: A low-noise quadrature phase I-Q modulator having a pair of Gilbert cell input stages driven by a feed voltage line and receiving in input respective square wave command signals coming from a local oscillator. The modulator comprises a transistor block with transistors connected to each cell and destined to carry out a voltage-current conversion of a signal in radio frequency received from the block itself; such block further including a single degeneration resistance.

Abstract: A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.

Abstract: A driver circuit drives a power element connected to an inductive load. The driver circuit includes an input terminal coupled to a control terminal of the power element through a trigger block, and a voltage regulator block having a circuit node coupled to a first supply voltage reference, as well as to a second supply voltage reference through a capacitor. A voltage comparator stage includes an operational amplifier having an inverting input connected to the circuit node and a non-inverting input is connected directly to a terminal of the power element, such as to the emitter terminal thereof. The operational amplifier also includes an output connected to the control terminal of the power element.

Abstract: A method is for driving an output buffer for outputting a datum of a certain voltage level with a certain slew-rate as a function of an input datum and a first enabling signal. The first enabling signal commands the buffer to a normal functioning state or to a high impedance state. The output buffer has an output stage controlled at least by a pull-up driving circuit and a pull-down driving circuit, and an enabling circuit input with the input datum and a second enabling signal and generating control signals. The control signals may be in phase or in phase opposition depending on whether the second enabling signal is active or disabled, and they are input into the respective driving circuits.

Abstract: A sensor having an array of photo sensitive elements for acquiring images of the passenger compartment in a motor vehicle and a circuit for processing the signals corresponding to the images generated by said photo sensitive elements. The processing circuit is configured according to a cellular neural network processing architecture of the image signals and can generate an output signal indicating the decision on whether to deploy an airbag to which the sensor is associated or to control the explosion of the airbag. Preferably, the photo sensitive array and the processing circuit are comprised on a single integrated component, preferably implementing CMOS technology.

Abstract: An amplifier having an input; an output supplying an output signal, and a feedback network connected between the input and the output, and a distortion detection circuit. The feedback network includes a first and a second feedback element arranged in series and forming an intermediate node supplying an intermediate signal in phase with the output signal in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit includes a phase-comparating circuit which detects the phase of the output signal and of the intermediate signal, and generates a distortion-indicative signal, when the intermediate signal is in phase opposition with respect to the output signal.

Abstract: A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator and a charge pump and having an output terminal; the voltage regulator having a regulation terminal connected to the output terminal, and an output supplying a control voltage; the read charge pump having an output connected to the output terminal and supplying a read voltage. The device further includes an enable circuit connected to the output and having a pump enable output connected to a charge pump enable terminal and supplying a pump enable signal. The pump enable signal is set at a first logic level so as to activate the charge pump when the read voltage is lower than a nominal value. In addition, the device generates a power-up sync signal which activates a read operation when the read voltage reaches its nominal value and a chip enable signal is set at an active value.

Abstract: An electronic circuit is for the gradual start-up of electric loads, particularly halogen lamps. The circuit may include a power device having an output terminal connected to the electric load and having at least one control terminal receiving a predetermined driving current value. The circuit may further include a comparator having a first input terminal coupled to the power device output and a second input terminal kept at a reference potential. The comparator output may be connected to a controlled switch inserted upstream of the control terminal to control the opening of the switch and adjust the start-up phase of the power device according to the value of the reference potential.

Abstract: A codifying and storing method for membership functions representing a membership degree of fuzzy variables defined within a universe of discourse which is discretized into a finite number of points is provided. The membership functions are quantized into a finite number of levels corresponding to a finite number of membership degrees and are stored by means of a characteristic value of each sub-set of values of fuzzy variables having for their image the same value of the membership degree corresponding to one of said levels. Also provided is a method for calculating the value of the membership degree of a fuzzy variable defined within a universe of discourse discretized into a finite number of points with reference to a membership function thereof, as well as to a circuit for calculating the membership degree of a fuzzy variable with reference to a membership function thereof.

Abstract: A VLSI architecture adapted to be implemented in the form of a reusable IP cell and including a motion estimation engine, configured to process a cost function and identify a motion vector which minimizes the cost function, an internal memory configured to store the sets of initial candidate vectors for the blocks of a reference frame, first and second controllers to manage the motion vectors and manage an external frame memory, a reference synchronizer to align, at the input to the estimation engine, the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller, and a control unit for timing the units included in the architecture and the external interfacing of the architecture itself.

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

Abstract: A capacitive high voltage generator comprising a first stage and a second stage respectively formed by a first basic block and a second basic block and a third basic block. Each basic block has a timing input, a first supply input, a second supply input and an output terminal and comprises: a buffer having a first terminal connected to the first supply input of the corresponding basic block, a second terminal connected to a ground terminal and an input terminal connected to the timing input of the corresponding basic block; a capacitor having a first terminal connected to an output terminal of the corresponding buffer and a second terminal connected, in a non-disconnectable way, to the output terminal of the corresponding basic block; a diode having a first terminal connected to the second supply input and a second terminal connected, in a non-disconnectable way, to the output terminal of the corresponding basic block.

Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.

Abstract: A converter that is directly connectable to an AC power source (e.g., the mains) includes a rectifier stage for rectifying a network voltage, a power factor correction pre-regulating circuit supplied with the rectified network voltage for producing a DC voltage of a predetermined nominal value on an output node, and a DC-DC converter. The DC-DC converter may be supplied on an input node thereof with the DC voltage of the predetermined nominal value for producing a regulated DC voltage on an output node thereof. The DC-DC converter may use a clock whose frequency is selected between at least one low and one high value by a selection signal. Furthermore, the converter may also include a stand-by circuit for producing the selection signal based upon the current delivered to the load.

Abstract: A method for the electrical and/or mechanical interconnection of components of a microelectronic system includes at least one first component and at least one second component to be connected, and at least one local Joule-effect micro-heater is incorporated in one of the first and second components at a respective soldering point therebetween. The method includes supplying electrical energy to the micro-heater to utilize the heat produced therefrom by the Joule effect to solder the first and second components at the respective soldering point.

Abstract: An output buffer, particularly for non-volatile memories, includes a push-pull output stage, a first data latch circuit receiving as an input data from an external data bus which connects at least one memory to the first data latch circuit, first and second activation paths for the activation of the push-pull stage, first and second circuits for enabling the push-pull stage, first and second circuits for disabling the push-pull stage, and second and third data latch circuits connected to the push-pull stage. More specifically, the first and second activation paths may be connected to the first data latch circuit. Furthermore, the first and second circuits for enabling the push-pull stage may be connected between the first data latch circuit and the push-pull stage.

Abstract: An integrated device comprises at least one circuit element and a plurality of trimming elements which can be connected selectively to the at least one circuit element in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element; the integrated device includes a plurality of electronic switches, each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements, respectively, and a memory for storing an indication of the states of the electronic switches and for operating each electronic switch in the first state or in the second state according to the indication stored.

Abstract: An impedance control circuit controls the impedance of an integrated output driving stage. The integrated output driving stage includes at least one enabling/disabling transistor and at least one driving transistor. The impedance control circuit includes a variable impedance circuit having an impedance that varies with the temperature in correlation with the impedance of the output driving stage. A control circuit is connected to the variable impedance circuit for generating at least one enabling/disabling signal for the at least one enabling/disabling transistor based upon a control signal correlated to the impedance of the variable impedance circuit. The impedance control circuit also includes a current generating circuit for applying to the variable impedance circuit a current which remains substantially stable as the temperature varies.

Abstract: A device for detecting load impedance having an analog circuit portion for detecting the impedance value of a load, and a digital circuit portion adapted to provide load impedance type information. The analog circuit portion having two power MOS transistors connected in series to each other and between a supply voltage and the ground, and a pair of mirror MOS transistors common-connected with their respective gate terminals to the gate terminals of the power MOS transistors. The digital circuit portion includes a first comparitor to determine whether the output current of an audio amplifier is higher or lower than a threshold value and a second comparitor to determine whether the output voltage of the amplifier is higher than a threshold voltage, a memory to store output signals of the first and second comparitors, and a logic circuit arranged in cascade with the memory to output a load-type indication signal.