Abstract: A method of driving an inductive load connected to an output of a power stage includes comparing a signal representative of an instantaneous value of current flowing through the inductive load with upper and lower thresholds during a switching cycle. The method also includes alternately performing a magnetization phase during which current is forced through the inductive load, and a demagnetization phase during which a load inductance of the inductive load discharges through at least one of a slow recirculation discharge current path and a fast recirculation discharge current path. Switching is performed between the slow and fast recirculation discharge current paths during each switching cycle as a function of the comparison for reducing a ripple on an output signal from the power stage.

Abstract: A method of assessing the offset on the output nodes of an amplifying channel includes generating a logic signal for signaling the existence of an offset having a level exceeding a window of permitted levels symmetric about the zero level. The window is defined by a negative limit value and by a positive limit value. The method includes establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency, sensing the rising edge of the timing pulse and setting a bistable circuit, and comparing the signal on the output nodes of the amplifiers channel with the window of permitted values. The bistable circuit is reset upon the occurrence, after the initial setting, of an output signal amplitude within the window of permitted values. Failure of the bistable circuit to reset before the end of the detection phase signals an excessive offset.

Abstract: Non linear circuit for open load control in Low-Side Driver type circuits, including at least two power transistors, scaled according to an area ratio 1 to M, with M>1, wherein the power transistor having the smaller area is controlled by a circuit input signal while the transistor having the larger area is controlled by an output value of an AND type logic gate, managed by a control circuit, that is regulated by the output value of a voltage sensor, placed in parallel with the power transistor having the larger area, and by the output value of a current sensor, placed in series with the power transistor having the smaller area, so that, when a current flowing in the power transistor having the smaller area is less than a predetermined value of the threshold current, the control circuit signals the open load on an output pin.

Abstract: A process for manufacturing a programmable non-volatile memory device having floating-gate MOS transistors, and first and second MOSFETs, the second MOSFETs capable of sustaining gate voltages higher than the first MOSFETs, by forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the first MOSFETs, and a third gate oxide layer for the second MOSFETs. The process includes: forming a first oxide layer over a substrate; selectively removing the first oxide layer from surface regions over the first MOSFETs, but not from surface regions over the floating-gate MOS transistors or the second MOSFETs; forming a second oxide layer over the first oxide layer and the regions over the first MOSFETs; removing the first and second oxide layer from a tunnel oxide region of the floating-gate MOS transistors; and forming a tunnel oxide layer over the second oxide layer and tunnel region oxide layer.

Abstract: A voltage boost device includes a first boost stage and a second boost stage connected to an input terminal and to an output terminal, the output terminal supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage is enabled in presence of the second logic level of the operating condition signal, and is disabled in presence of the first logic level of the operating condition signal; the second boost stage is controlled in a first operating condition in presence of the first logic level of the operating condition signal, and is controlled in a second operating condition in presence of the second logic level of the operating condition signal.

Abstract: A nonvolatile memory device has a signature code generator generating an new signature code as a function of data read from the cell array and the previously calculated signature code. Data are read in sequence, using an internal clock generated by an internal clock oscillator. In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code is variable in dynamic way; at the end of memory scanning, the signature code is compared to an expected result. Thus, testing may be performed at Wafer Sort Test Level, reading the memory cells at the memory operative speed, so as to ensure an early, fast and thorough detection of faults.

Abstract: An enabling circuit for an output buffer in a memory having separate reading paths includes an output buffer driver for driving loading of the output buffer, and an output enabling circuit for enabling the output buffer driver. A timing circuit controls the switching of the output enabling circuit. A switching circuit is responsive to a read mode signal for providing a stimulus signal for loading of the output buffer and for performing a switching between the separate reading paths of the memory.

Abstract: An interface between a semiconductor substrate/dielectric layer is characterized through measurements of a photocurrent. The photocurrent is induced in the semiconductor substrate by scanning a certain area of the interface with a laser beam and which is collected via a Schottky contact. The Schottky contact is established by inversely biasing a first electrolyte with respect to a potential of the bulk of the semiconductor substrate. The first electrolyte is capable of etching any native or thermal oxide that may exist on the contact area with the semiconductor substrate. The surface potential of the semiconductor substrate/dielectric interface is controlled by a gate electrode established on the dielectric layer by way of a second electrolyte. The second electrolyte is not aggressive to the dielectric material and is biased by an electrode immersed therein with respect to the potential of the bulk of the semiconductor substrate.

Abstract: A non-volatile memory cell and a manufacturing process therefor are discussed. The cell is integrated in a semiconductor substrate and includes a floating gate transistor having a first source region, first drain region, and gate region projecting over the substrate between the first source and drain regions. The cell also includes a selection transistor having a second source region, second drain region, and respective gate region, projecting over the substrate between the second source and drain regions. The first and second regions are lightly doped and the cell comprises mask elements.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: A driver circuit drives a power element connected to an inductive load. The driver circuit includes an output terminal, and a first current generator is connected between a voltage reference and the output terminal for providing a first charge current to a control terminal of the power element, which is connected to the output terminal. The driver circuit also includes a second current generator connected in parallel with the first current generator. The second current generator is connected between the voltage reference and the output terminal, and provides the control terminal with a second charge current dependent on a voltage present at the input terminal. The input terminal is connected to a conduction terminal of the power element.

Abstract: A method of forming metal connection elements in integrated circuits formed on adjacent areas of a wafer includes forming a conductive seed layer on a substrate of the wafer. A first mask covers the integrated circuits and leaves exposed areas of the seed layer overlying predetermined scribe lines used for separation of the integrated circuits. Using the seed layer as a cathode, a metal is deposited by an electrochemical process on exposed areas of the seed layer. The first mask is removed and a second mask is formed, leaving predetermined areas of the seed layer exposed. Using the seed layer as a cathode a metal is deposited on the exposed predetermined areas by an electrochemical process. The second mask is then removed. Connection elements of uniform thickness throughout the substrate are produced with the use of a very thin seed layer.

Abstract: There is provided an adjustable harmonic distortion detector that includes a clock signal source, means for the detection of a first period of evaluation, and means for the detection of a second period of evaluation. The detector has the characteristic that a first block memorizes a number equal to the clock pulses present in the first period of evaluation, a multiplier block performs a multiplication between the number stored in the first block and a multiplicative factor during the second period of evaluation, and a second block memorizes the outcome. The second block is adapted to generate an output signal when the outcome in the second block is equal to zero.

Abstract: A method of controlling the movements of a multi-actuator electromechanical system having a matrix of locally interconnected analog cells associated therewith is provided. Each cell represents a hardware implementation of a model of fuzzy inference rules. The model includes a fuzzy circuit architecture which may be implemented in an integrated circuit with VLSI CMOS technology that generates and controls a reaction diffusion mechanism typical of auto-waves using a fuzzy neural network. The fuzzy neural network defines the functional relationships that may duplicate simultaneous reaction diffusion equations. The duplication of the simultaneous reaction diffusion equations is provided using two sets of fuzzy rules processing, in a linguistic manner, the state variables of the cells. An oscillatory type dynamic is imposed on each cell where two dynamic processes having different kinetic characteristics coexist.

Abstract: The method is intended for manufacturing a microintegrated structure, typically a microactuator for a hard-disk drive unit and includes the steps of: forming interconnection regions in a substrate of semiconductor material; forming a monocrystalline epitaxial region; forming lower sinker regions in the monocrystalline epitaxial region and in direct contact with the interconnection regions; forming insulating material regions on a structure portion of the monocrystalline epitaxial region; growing a pseudo-epitaxial region formed by a polycrystalline portion above the structure portion of the monocrystalline epitaxial region and elsewhere a monocrystalline portion; and forming upper sinker regions in the polycrystalline portion of the pseudo-epitaxial region and in direct contact with the lower sinker regions. In this way no PN junctions are present inside the polycrystalline portion of the pseudo-epitaxial region and the structure has a high breakdown voltage.

Abstract: An integrated device in emitter-switching configuration is described. The device is integrated in a chip of semiconductor material of a first conductivity type which has a first surface and a second surface opposite to each other. The device comprises a first transistor having a base region, an emitter region and a collector region, a second transistor having a not drivable terminal for collecting charges which is connected with the emitter terminal of the first transistor, a quenching element of the first transistor which discharges current therefrom when the second transistor is turned off. The quenching element comprises at least one Zener diode made in polysilicon which is coupled with the base terminal of the first transistor and with the other not drivable terminal of the second transistor.

Abstract: A set of sampling capacitors weighted according to a binary code is charged through a first capacitive unit, whose capacitance is equal to the sum of the capacitances of the set, at a voltage Vcm−Vin/2. The conversion is carried out by an SAR process by a comparator and a logic unit which operates the switches associated with the capacitors. The final position of the switches is loaded into a register which supplies the digital output signal. To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units are provided, with the same capacitance as the first capacitive unit. These make it possible to prevent all the disturbances at the input of the comparator in common mode and therefore without any effect on the output.

Abstract: The switch circuit receives a first supply voltage and a second supply voltage different from each other; a control input receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage supplied by the second supply voltage and defining the output of the circuit; a feedback inverter stage supplied by the second supply voltage and including a top transistor and a bottom transistor defining an intermediate node and having respective control terminals. The control terminal of the top transistor is connected to the output node, the control terminal of the bottom transistor is connected to the control input, and the intermediate node is connected to the input of the driving inverter stage. An activation element helps switching of the intermediate node from the second supply voltage to ground; current limiting transistors are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.

Abstract: A control circuit for controlling current of batteries at the end of the charging phase, especially for lithium batteries, including an input/output circuit, placed between a battery charger and a battery, and an output stage, including two transistors, wherein the resistance of one of the two transistors is modulated to increase the value of the total resistance and to cause a lower turning off current of said output stage.

Abstract: An infrared detector device having a PN junction formed by a first semiconductor material region doped with rare earth ions and by a second semiconductor material region of opposite doping type. The detector device comprises a waveguide formed by a projecting structure extending on a substrate, including a reflecting layer and laterally delimited by a protection and containment oxide region. At least one portion of the waveguide is formed by the PN junction and has an end fed with light to be detected. The detector device has electrodes disposed laterally to and on the waveguide to enable efficient gathering of charge carriers generated by photoconversion.