Abstract: A method of improving the signal/noise ratio of a sigma-delta modulator during the re-establishment of its stability that includes: defining a bit sequence corresponding to a state of instability of the modulator, monitoring the flow of bits output by the modulator to check whether it contains the instability bit sequence, and resetting the modulator to zero if the instability bit sequence is detected at the output. To ensure a high signal/noise ratio of the modulator even during the detection and re-establishment of stability, the method also includes: delaying the flow of bits output by the modulator at least for the time required to detect the instability bit sequence and modifying the output bit sequence during the delay period by replacing it with a predetermined bit sequence.

Abstract: A switching regulator circuit produces a varying reference voltage with temperature and includes at least one band-gap generator for supplying a power stage through an error amplifier and a comparator. The error amplifier is also supplied a regulated voltage which may be produced by the regulator itself. The at least one band-gap generator includes a plurality of band-gap generators being supplied by the regulated voltage and input a fraction of the regulated voltage through a voltage divider. The respective outputs of the band-gap generators are connected to a logic network which has an output connected to the power stage. The error amplifier and comparator may be included within each respective band-gap generator.

Abstract: A nonvolatile memory having a NOR architecture has a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines; and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

Abstract: A delay-locked loop circuit (DLL) includes a delay line with a delay which can be varied in a controlled manner to delay a periodic input signal having a period T, and a control circuit for controlling the delay line to lock the delay to the period T. The delay line supplies to the control circuit a plurality of periodic signals each delayed relative to the periodic input signal by a respective fraction of the delay. The control circuit includes a sequence-detector circuit which can periodically detect in the delayed signals characteristic sequences of digital values indicative of the delay. The control circuit can bring about a reduction or an increase in the delay for locking to the period T based upon the detected types of characteristic sequences.

Abstract: Relaying on a temporal correlation among successive pictures and using a hierarchical recursive motion estimation algorithm, the hardware complexity of video coders complying with the MPEG-2 standard can be significantly reduced without an appreciable loss of quality of the video images being transferred. Relaying on a temporal correlation among successive pictures is also performed on a spatial correlation of motion vectors of macroblocks of the currently processed picture.

Abstract: To increase the facing surface and thus the coupling between the floating gate and control gate regions of a memory cell, the floating gate and control gate regions have a width that is not constant in different section planes parallel to a longitudinal section plane extending through the source and drain regions of the cell. In particular, the width of the floating gate and control gate regions is smallest in the longitudinal section plane and increases linearly in successive parallel section planes moving away from the longitudinal section plane.

Abstract: A method of equalizing a read channel of a mass magnetic memory device comprises attenuating the low frequencies of the spectrum of the analog signal originating from an electromagnetic read transducer without boosting the high frequency harmonic components of the spectrum. The low frequencies of the spectrum of the analog input signal are attenuated with a low pass filter of an order in a range from 6 to 8 and a boost is implemented by introducing two real and opposed zeroes in the transfer function of the filter without altering the group delay.

Abstract: A memory device having an associative memory for the storage of data belonging to a plurality of classes. The associative memory has a plurality of memory locations aligned along rows and columns for the storage of data along the rows. Each memory row has a plurality of groups of memory locations, each storing a respective datum, wherein groups of memory locations adjacent along one and the same row store data belonging to different classes. Groups of memory locations adjacent in the direction of the columns and disposed on different rows store data belonging to one and the same class. Each class has data having a different maximum lengths. The device is particularly suitable for the storage of words belonging to a dictionary for automatic recognition of words in a written text.

Abstract: A method of making an integrated circuit that is resistant to an unauthorized duplication through reverse engineering includes forming a plurality of false contacts and/or false interconnection vias in the integrated circuit. These false contacts and/or false interconnection vias are connected as true contacts and true interconnection vias by lines patterned in a metallization layer deposited over an insulating dielectric layer or multilayer through which the true contacts and/or the true interconnection vias are formed. False contacts and false vias extend in the respective dielectric layers or multilayers to a depth insufficient to reach the active areas of a semiconductor substrate for false contacts, or to a depth insufficient to reach a layer of conductive material below the dielectric layers or multilayers for interconnection vias.

Abstract: A circuit for the speed recovery of a direct current motor comprises an output stage, that includes a first couple of transistors and a second couple of transistors, and first means, for detecting a current circulating in said motor. The circuit has the characteristic of comprising second means, suitable for activating said second couple of transistors of said output stage for a determined first time period so as to short-circuit said motor, and at the end of said first time period said second means being suitable for unbalancing said output stage so as to force the maximum current circulating for a determined second time period in function of the value detected by said first means during said first time period so as to stop said motor.

Abstract: The device can be used for generating, in the framework of a CDMA communications terminal, both Walsh-Hadamard channeling codes and OVSF channeling codes. The device comprises a code generator preferably configured for generating Walsh-Hadamard codes. When the device is used for generating Walsh-Hadamard codes, the corresponding index values, applied to an input of the device, are sent to the input of the code generator. Generation of OVSF codes envisages, instead, that the corresponding indices, sent to an input of the device, undergo mapping, which enables generation, starting from the OVSF code, of the corresponding index identifying a string of symbols that is identical within the Walsh-Hadamard code. In this way each string of OVSF code symbols is generated, so producing, by means of the code generator, the generation of the identical string of symbols included in the Walsh-Hadamard code.

Abstract: Presented is a process for manufacturing circuit structures of the SOI type integrated on a semiconductor substrate having a first type of conductivity. The process includes forming at least one well with a second type of conductivity in the semiconductor substrate and forming a hole within the well. The hole is then coated with an insulating coating layer, and an opening is formed through the insulating coating layer at the bottom of the hole. The hole is then filled with an epitaxial layer grown from a seed that was made accessible through the opening in the hole.

Abstract: The memory cell is of the type with a single level of polysilicon, and is produced in a substrate of semiconductor material with a first type of conductivity, and comprises a control gate region with a second type of conductivity, formed in the substrate in a first active region; regions of source and drain with the second type of conductivity, formed in the substrate in a second active region; and a floating gate region which extends transversely relative to the first and the second active regions. The control gate region is surrounded by a first well with the first type of conductivity, which in turn is surrounded, below and laterally, by a third well with the second type of conductivity. The regions of source and drain are accommodated in a second well with the first type of conductivity, which in turn is surrounded below and laterally by a fourth well with the second type of conductivity.

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin

Abstract: A process for manufacturing a ferroelectric capacitor includes the steps of forming a first plate of a noble metal, preferably platinum, above an insulating layer of a wafer; forming a dielectric material layer with ferroelectric properties; and forming a second plate of a noble metal above said dielectric material layer. The first plate and the second plate are formed by electrochemical deposition of a metal.

Abstract: An electronic circuit is for optimizing or reducing switching losses in current-driven power devices and includes a switching power device connected to an electric load. The power devices has at least one control terminal arranged to receive a predetermined drive current value produced by a first current generator. The control terminal also receives an additional drive current portion produced by a second independent current generator. Advantageously, the electronic circuit includes a control circuit for controlling a switch connected between the second current generator and the control terminal of the switching power device during the turn-on and turn-off phases of the power device.

Abstract: There is provided a digital data transmission system that includes a first unit transmitting a first MLT3 signal, a second unit receiving the first MLT3 signal, and transformers. The second unit includes an equalizer receiving the first MLT3 signal and outputting a second MLT3 signal that is input to a recovery module for the transmitted digital data, and a device placed in feedback to the equalizer. The device receives the second MLT3 signal and outputs a third low frequency signal that is added to the first MLT3 signal. The device has a translation block for the up or down or no translation of the second MLT3 signal according to the low or high or intermediate value of such signal, and a low pass filter receiving the signal output from the translation block and outputting the third signal containing the low frequency component of the second MLT3 signal.

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a scounter.

Abstract: A rectifying integrator of an input signal with full output dynamics, relative to a voltage reference intermediate with respect to the dynamics of the input signal, includes a first line of integration having at least one integrator for integrating that portion of the input signal that exceeds the voltage reference, and includes a hold capacitor coupled in cascade to the integrator. The rectifying integrator includes a second line of integration, identical to the first line of integration, for integrating that portion of the input signal that remains below the voltage reference. An adder output stage generates an output signal equal to the difference between the voltages existing on the hold capacitors of the first and second lines of integration.