Abstract: A method is for implementing at least one clock tree in a synchronous digital electronic circuit. The method may include selecting an interchangeable programmable delay buffer stage, calculating an expected skew based upon the selected interchangeable programmable delay buffer stage, and interchanging the selected interchangeable programmable delay buffer stage with another if the expected skew is different from a desired skew. A related synchronous digital electronic circuit includes a plurality of clock trees, and an interchangable programmable delay buffer stage connected to each of the clock trees.

Abstract: The memory device comprises a memory array having an organization of the type comprising global word lines and local word lines, a global row decoder addressing the global word lines, a local row decoder addressing the local word lines, a global power supply stage supplying the global row decoder, and a local power supply stage supplying the local row decoder.

Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.

Abstract: An inertial sensor having an inner stator and an outer rotor that are electrostatically coupled together by mobile sensor arms and fixed sensor arms. The rotor is connected to a calibration microactuator comprising four sets of actuator elements arranged one for each quadrant of the inertial sensor. There are two actuators making up each set. The actuators are identical to each other, are angularly equidistant, and each comprises a mobile actuator arm connected to the rotor and bearing a plurality of mobile actuator electrodes, and a pair of fixed actuator arms which are set on opposite sides with respect to the corresponding mobile actuator arm and bear a plurality of fixed actuator electrodes. The mobile actuator electrodes and fixed actuator electrodes are connected to a driving unit which biases them so as to cause a preset motion of the rotor, the motion being detected by a sensing unit connected to the fixed sensor arms.

Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.

Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Abstract: A digital-analog converter having a sigma delta cascade modulator with two outputs, particularly a third order sigma delta modulator 2+1.

Abstract: A method is for compressing a digital image that is made up of a matrix of elements, with each element including a plurality of digital components of different types for representing a pixel. The method includes splitting the digital image into a plurality of blocks, and calculating for each block a group of DCT coefficients for the components of each type, and quantizing the DCT coefficients of each block using a corresponding quantization table scaled by a gain factor for achieving a target compression factor. The method further includes determining at least one energy measure of the digital image, and estimating the gain factor as a function of the at least one energy measure. The function is determined experimentally according to the target compression factor.

Abstract: An interconnect system adapted for acting as a data path for transferring data fields on a bus between a plurality of initiators and targets operates in such a way that each data field is transferred during a respective cycle of a corresponding clock signal. The system is configured in such a way that the said data fields are divided into a first and a second part. Similarly, the cycle of the clock signal is divided into a first and a second part. The first and the second part of each data field are transferred, respectively, during the first and the second part of the cycle of the clock signal. Data fields having a size of 128 bits, for example, can thus be transferred on a 64-bit data path structure without any negative effect on the system performance and without the necessity of increasing the clock frequency; this facilitates the integration of the system on a chip.

Abstract: A self-disabling and self-recovering converter includes a transformer connected to a power source and has an auxiliary winding for providing a self-supply voltage after start-up, and an integrated circuit having circuitry and a plurality of pins connected thereto. The converter also includes at least one external line and a sensor connected thereto for an electrical or physical quantity to be monitored. The at least one external line is biased through a first pin with the self-supply voltage, and is functionally coupled to a second pin when a threshold is surpassed. A sectionable voltage clamp chain is connected between the auxiliary winding and a voltage reference. A self-recovery circuit having a first input is connected to the auxiliary winding and a second input is connected through the second pin to the at least one external line.

Abstract: A memory circuit having a first and a second block of memory cells with rows that cross both blocks and columns in each of the two blocks. A word decoder selects one of the rows, and a column decoder selects a set of columns from the first and second blocks. An address splitter passes relative portions of an address to each decoder. In one embodiment, the address splitter passes the most significant bits of the address to the word decoder and passes the remaining bits to a portion of the column decoder coupled to the first block only. The address splitter also modifies the remaining bits, using a bit subtractor, and passes them to a portion of the column decoder coupled to the second block only. A method of operating a memory device is provided that includes accepting an address at an input address circuit and then determining whether the address is for data in the first block or in the second block. This information is assessed by comparing it to the number of memory cells in the first block.

Abstract: A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.

Abstract: A DC-DC converter having a current error amplifier and a voltage error amplifier connected in parallel to control the charging of the battery and a gradual turning off circuit for turning off gradually the current error amplifier in a battery charging end phase. In this way, the DC-DC converter is able to supply to the battery a battery charging current that remains constant until the battery full charge voltage is reached.

Abstract: Method for localizing point defects causing column leakage currents in a non-volatile memory device including a plurality of memory cells arranged in rows and columns in a matrix structure, source diffusions, and metal lines which connect said source diffusions to each other. Such a method includes the steps of: modifying the memory device in order to make source diffusions independent of each other and each one electrically connected to a respective row; sequentially biasing the single columns of the matrix; localizing the column to which at least one defective cell belongs, as soon as the leakage current flow occurs in the biased column; by keeping biased the localized column, biasing sequentially the single rows of the matrix to the same potential as that of the localized column; localizing a couple of cells, wherein at least one of them involves the point defects, as soon as the leakage current flow does not occur.

Abstract: A method is for compressing a digital image including a matrix of elements, with each element including at least one component of a different type for representing a pixel. The method includes splitting the digital image into a plurality of blocks, and calculating for each block a group of discrete cosine transform (DCT) coefficients for the components of each type, and quantizing the DCT coefficients of each group using a corresponding quantization table scaled by a gain factor for achieving a target compression factor. The method also includes further quantizing the DCT coefficients of each group using the corresponding quantization table scaled by a pre-set factor, and arranging the further quantized DCT coefficients in a zig-zig vector.

Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.

Abstract: An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of the banks, and a carry calculation network. The interleaved memory operates in a burst access mode enabled by an enabling signal. The carry calculation network includes an ordered group of independent carry generators. Each independent carry generator includes a certain number of stages, with each stage having inputs receiving its own enabling bit and a number of consecutive bits of a row of the bank equal to the number of stages, orderly starting from the least significant bit. The enabling bit of the first carry generator of the ordered group is the enabling signal, and the enabling bit of any other carry generator of the ordered group is the logic AND of the enabling signal and of the input bits of the preceding carry generator of the ordered group.

Abstract: A method is provided for carrying out a trimming operation on an integrated circuit having a trimming circuit portion which includes memory elements and a modification circuit for modifying the state of the memory elements, at least a first input or supply pin, an output pin, and a second supply pin. According to the method, a single pin is enabled to receive trimming data by biasing the pin to outside its operating range. A clock signal is obtained from a division of the bias potential of the pin, and the logic value of the trimming data is obtained from a different division of the bias potential of the pin. Serial acquisition of the data is enabled in accordance with the clock signal, and the data is transferred to the modification circuit.

Abstract: A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells is presented. In the memory device, the matrix is formed on a semiconductor substrate with a number of continuous bit lines extending across the substrate as discrete parallel strips. The process begins by growing an oxide layer over the matrix region and depositing over the semiconductor throughout a stack structure which comprises a first conductor layer, a first dielectric layer, and a second conductor layer. Then a second dielectric layer is deposited over the stack structure, and floating gate regions are defined by photolithography using a mask of “POLY1 along a first direction”, to thereby define in the dielectric layer, a plurality of parallel strips which delimit a first dimension of floating gate regions.

Abstract: When programming, for each programming pulse, a threshold voltage whose value is increased with respect to the previous programming pulse is applied to the gate terminal of each cell to be programmed. After an initial step, the increase of threshold voltage of the cell being programmed becomes equal to the applied gate voltage increase. In order to reduce the global programming time, keeping a small variability interval of threshold voltages associated with each level, to pass from a threshold level to a following one, each cell to be programmed is supplied with a plurality of consecutive pulses without verify, until it is immediately below the voltage level to be programmed, and then a verify step is performed, followed by subsequent programming and verify steps until the cell to be programmed reaches the desired threshold value.