Abstract: In order to estimate power consumption, over a given time interval, of digital circuits described at the level of functional elements provided with input/output terminals associated additional elements are emulated at the hardware level. The said additional emulated elements are able to detect, during said time interval, at least one signal indicative of the behavior of the functional element associated during hardware emulation of the circuit. Preferably the number of transitions performed during the aforesaid time interval of the associated functional element is recorded, as well as the fraction of time in which the state of said functional element is stable. The value of said signals is acquired to perform an estimation of the power consumption of the functional element during the aforesaid time interval.

Abstract: The present invention relates a current zero crossing detecting circuit including a PWM driving half bridge circuit, which generates an output signal (OUT) and a signal synchronous with the high impedance condition of said PWM driving half bridge circuit. Said inventive circuit has the characteristic of comprising detecting means (DFLIP, COMP) synchronous with said signal synchronous with the high impedance condition of said PWM driving half bridge circuit and said output signal (OUT), and said detecting means generating a direction signal (DIR_COR) showing the current direction flowing in said pulse width modulation circuit.

Abstract: A method for detecting a zero-cross event of an induced back electromotive force (BEMF) or of a nullification instant of a periodic current in a PWM driven winding, by circuits generating an analog signal representative of the induced BEMF or of the nullification instant of the periodic current, comparing the analog signal with zero and producing a first logic signal, generating a PWM driving signal, and storing a time between two consecutive zero-cross events, is provided. The method may include storing a time between a last two zero-cross events and synchronizing the PWM driving signal from a last zero-cross event having a duration equal to a difference between an established time based upon the stored time interval and a first time. If a new zero-cross event is not detected within the established time, switching of the PWM driving signal may be disabled for a time having a maximum duration equal to a second time or until a new zero-cross event is detected.

Abstract: A CMOS technology voltage booster having plurality of charge-pump stages cascade connected together and driven by a plurality of phases, each stage having a terminating input node and a terminating output node, with at least one transistor connected therebetween that has its control terminal connected to an internal circuit node of the same stage and applied one of the phases. This voltage booster further includes a pair of additional circuit elements for transferring, onto the internal node, a potential exceeding the voltage at the input node by at least one threshold. A first of the additional elements is essentially a MOS transistor having its control terminal connected to the control terminal of that transistor that is connected between the input and the output of the stage, while the second additional element is an auxiliary capacitor having one end connected directly to the first additional element and connected to the internal node through a transistor.

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Abstract: Described in the disclosure is a method for fabricating high-capacitance capacitive elements that are integrated in a semiconductor substrate. First a dielectric layer is formed over the surface of the substrate and a metal layer is deposited thereon. The metal layer is patterned and etched to form lower plates of the capacitive elements, as well as to form interconnection pads. Then, an intermediate dielectric layer is deposited on the lower plates and interconnection pads, and over the entire exposed surface of the substrate. Following that, a sacrificial conductive layer is deposited onto the intermediate dielectric layer, and the upper plates of the capacitive elements are formed out of the sacrificial conductive layer. Then, an upper dielectric layer is formed over the entire semiconductor, and openings are formed in this layer for the upper plates and the interconnection pads.

Abstract: A process for forming floating gate non-volatile memory cells in a cell matrix with associated control circuitry comprising both N-channel and P-channel MOS transistors is provided. The process includes forming active areas in a substrate for the cell matrix and the associated control circuitry. A first thin oxide layer and a first polysilicon layer are deposited on the active areas to produce floating gate regions of the memory cells, and a second dielectric layer is deposited on the active areas. A second polysilicon layer is then deposited on the active areas. A masking and etching step is performed for exposing the substrate for the associated control circuitry followed by the deposition of a third polysilicon layer. The third polysilicon layer is defined to produce the gate regions of the transistors for the associated control circuitry while the third polysilicon layer is removed from the cell matrix.

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P−. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

Abstract: A driving circuit for piezoelectric actuators comprises a chip of semiconductor material integrating both an interface circuit receiving at input a control signal generated by a control logic unit, and a power circuit driving the piezoelectric actuators. The power circuit is directly connected to the output of the interface circuit.

Abstract: A noise compensating device in a discrete time control system, such as a R/W system for hard disks, including: a control loop generating a first timing signal, a signal indicative of a quantity to be controlled, and a control signal, which have a first frequency; and an open loop control line which generates a compensation signal synchronous with the control signal and includes a sensor. The sensor includes a sensing element, generating an analog signal, an acquisition stage, connected to the sensing element and generating a disturbance measure signal correlated to the analog signal and synchronous with the control signal, and a synchronization stage. The synchronization stage includes a frequency generator having an input receiving the first timing signal and a first and a second output connected to the acquisition stage and generating, respectively, a second timing signal and a third timing signal.

Abstract: A control device for a vehicle engine includes a memory unit for storing engine configuration parameters, a processing unit for sending control signals to the engine in accordance with the configuration parameters, and an input/output unit connectible to an external computer to modify the configuration parameters. The control device includes a first portion and a second portion of the memory unit, with each portion being alternately used in an active state for storing a current version of the configuration parameters or in an inactive state for the writing of a new version of the configuration parameters. The processing unit accesses the portion which is in the active state for reading, and the input/output unit accesses the portion which is in the inactive state for writing. An interconnection unit selectively switches one of the portions to the active state and the other of the portions to the inactive state.

Abstract: A method for forming an conductive interconnection in an electronic semiconductor device includes forming a layer of insulating material on a substrate of semiconductor material having a contact region therein, and forming a first opening through the layer of insulating material to expose the contact region. The first opening is filled with a material to form a first connection element. A first layer comprising a first removable conductive material is formed adjacent the layer of insulating material and the first connection element. The method further includes forming a second opening in the first layer to expose the first connection element, and filling the second opening with the material to form a second connection element. The first removable conductive material is removed except for a portion underlying the second connection element to expose the layer of insulating material. The areas left free after removing the first removable conductive material are filled with a dielectric material.

Abstract: A field effect transistor having a variable doping profile is presented. The field effect transistor is integrated on a semiconductor substrate with a respective active area of the substrate including a source and drain region. A channel region is interposed between the source and drain regions and has a predefined nominal width. The effective width of the channel region is defined by a variable doping profile.

Abstract: Fully-differential, switched-capacitor circuit having a first and second input terminal, and including: an operational amplifier having a first and a second differential input, a first and a second output terminal and a bias control terminal; a feedback network, connected between the differential outputs and the input terminals, and having intermediate nodes connected to the differential inputs of the operational amplifier; and a control circuit, including a detection network and an error amplifier. The error amplifier has a first input receiving a desired common-mode voltage, and an output connected to the bias control terminal and supplying a control voltage. The detection network has a first and a second input connected directly, respectively, to the second input terminal of the operational amplifier, and an output connected to a second input of the error amplifier, and supplying a common-mode drive voltage.

Abstract: A non-volatile memory device with configurable row redundancy includes a non-volatile memory having a matrix of memory cells and a matrix of redundant memory cells, both organized into rows and columns. The memory device also includes row and column decoding circuits; read and modify circuits for reading and modifying data stored in the memory cells; and at least one associative memory matrix, also organized into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix. The memory device further includes a circuit for recognizing and comparing selected row addresses with faulty row addresses contained in the associative memory matrix, such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and a configuration register, also comprising a matrix of non-volatile memory cells, and associated control circuits.

Abstract: A positioning system for a read/write head of a disk drive includes a rotatable data disk, a read/write head movable over the disk, a voice coil motor (VCM) connected to the head and a source of digital position signals. A control circuit includes means for generating a VCM control current, a sensor for sensing the VCM current and an amplifier having an inverting input connected to a reference voltage source through a resistor and to a sensor output, a non-inverting input connected to the source of digital position signals through a DAC and an output connected to an input of the drive means.

Abstract: Presented is a circuit and method capable to digitally control and, in particular, to control the switching of one or two MOSFETs used as rectifiers in switched mode power supply isolated topologies. Basic circuit implementation of the presented technique is also introduced. A controller has a fixed frequency square wave signal main clock input, generically switching from a low to a high value in two different time intervals. The controller has one or two square wave outputs, swinging from low to high in phase or in opposite with respect to the clock signal. The digital control method is able to generate output signals timed to anticipate output transitions from high to low level with respect to the clock signal transitions. In the control scheme, one or two other secondary inputs set the amount of anticipation time of the respective transitions of the outputs.

Abstract: A method of assessing the neuro-psycho-physical condition of a person includes acquiring, by a self-contained hand held instrumentation, reaction times, execution times and ergometric data of actions performed by the person carrying out a certain test. This test includes processing the time data and the ergometric data for calculating the power exerted in performing each action. Data on the reaction time and the exerted power is processed on the basis of certain software to produce information on the neuro-psycho-physical condition. The ergometric data and reaction time data are processed by a fuzzy logic processor. The hand held instrument may optionally include also motion and voice articulation classifiers.

Abstract: Presented is a high-efficiency CMOS voltage shifter including a differential cell circuit portion powered between first and second supply voltage references, and a first pair of transistors connected into a cascode configuration. Also included is a first divider of the first supply voltage reference for generating a reference voltage value on a first internal circuit node, which is connected to the gate terminals of the transistors in the first pair. The voltage shifter further includes a second divider of the first supply voltage reference for controlling the value of the reference voltage by means of a control circuit portion acting on the first divider.

Abstract: An electronic thermal protection circuit is for high currents which can occur in the start-up phase in lighting converters. The circuit is associated with a power device having an output terminal connected to an electric load and at least one control terminal receiving a predetermined driving current value by a driving circuit portion. Advantageously, an integrated temperature sensor is provided to detect the temperature of the power device, and an output stage is connected downstream of the sensor to switch off the driving circuit portion when a predetermined operation temperature is exceeded.