Abstract: An alphanumeric character image recognition system includes a first stage comprising at least a first, second and third digital image signal processing network having each at least one input terminal and at least one output terminal and said networks being designed to process image information from digital image signals, and comprising at least a first, second and third memory register having each at least one input terminal and at least one output terminal and the input terminals of the first, second and third memory registers being connected to the output terminal of the first network, the output of the second network and the output terminal of the third network respectively and said memory registers being designed to contain the image information processed by the first, second and third digital image signal processing networks, and a second stage characterized in that said second stage comprises at least one first and one second classifier network having each at least one first and one second input termina

Abstract: A start-up procedure for a multiphase brushless motor to be accelerated until reaching a certain speed includes determining the starting position of the rotor and performing an excitation phase including forcing a drive current in the phase windings of the motor for an established period of time. This is done according to a switching sequence for inducing a rotation in the desired direction. Furthermore, the method may include sensing the position reached by the rotor at the end of each excitation phase. The start-up procedure is eventually interrupted when the established speed has been reached or exceeded. Additionally, the duration of a next phase of excitation may be increased or reduced, and the switching sequence may be modified, based upon the number of consecutive times in which the current position is found to be the same or different from the previously detected position, respectively.

Abstract: A decoupling circuit for decoupling conduction lines from each other, the circuit including at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal. The decoupling circuit includes at least one protection circuit inserted between the control terminal and at least one of the conduction lines, and including at least one protection transistor connected to the control terminal and to the at least one conduction line, and configured to take in a disturbing signal passing through the pass gate element (N1) to properly decouple the conduction lines from each other on the occurrence of a disturbing condition.

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

Abstract: The ROM memory cell, not decodable by visual inspection comprises a substrate of semiconductor material having a first conductivity type, in particular P−. A first MOS device having a first threshold voltage is formed in a first portion of the substrate, and a MOS device having a second threshold voltage, greater than the first threshold voltage, is formed in a second portion of the substrate adjacent to the first portion. The second MOS device is a diode reverse biased during a reading phase of the ROM memory cell and comprises a source region having the first conductivity type and a drain region having a second conductivity type. The source region has a level of doping higher than that of the substrate.

Abstract: A lead-frame for semiconductor devices having a mold with at least one air vent for the resin to seep out of during its injecting into the mold, the air vent being positioned between the upper and lower surface of the frame, wherein the frame provides a through hole positioned at the outlet of the air vent so that, when the resin has solidified, it forms a flash which is in coherence with the surface of the frame.

Abstract: To reduce the risk of breakage of the moving parts of an integrated microstructure during manufacture steps causing mechanical stresses to the moving parts, a temporary immobilization and support structure is formed, whereby a moving region of the microstructure is temporarily integral with the fixed region. The temporary structure is removed at the end of the assembly operations by non-mechanical removal methods. According to one solution, the temporary structure is formed by a fusible element removed by melting or evaporation, by applying a sufficient quantity of energy thereto. Alternatively, a structural region of polymer material is formed in the trench separating the moving part from the fixed part, or an adhesive material layer sensitive to ultraviolet radiation is applied.

Abstract: Presented is a low-voltage automatic lock-up biasing circuit with input terminals that accept input voltages, and with an internal node coupled to both input terminals an which takes take the highest of the voltage values applied to the input terminals. This circuit uses a comparator having respective inputs connected to the input terminals and with an output connected to a level shifter. Outputs of the level shifter are coupled to respective enable elements connected between each input terminal and the internal node. The enable elements are driven each by a respective output of the level shifter.

Abstract: Presented is an energy efficient charge pump, that includes at least two stages. Each stage has input and output nodes, which correspond to terminals of a first transistor. A boost capacitor is tied to the input node, and a second capacitor is tied to an internal node, which is also the gate terminal of the first transistor. A second transistor is located between the input node and the internal node, and has a gate coupled to the output node. A driving signal generator generates ramped voltage driving signals and non-ramped voltage driving signals. Attached to the driving signal generator is a phase driver that applies the ramped voltage driving signals to the boost capacitor and applies the non-ramped voltage driving signals to the second capacitor. Also presented also is method of driving a charge pump, such as the one described above, where the boost capacitor is driven with a ramped voltage signal, while the second capacitor is driven with a non-ramped voltage signal.

Abstract: A direct-comparison reading circuit for a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, and at least one bit line, includes at least one array line, selectively connectable to the bit line, and a reference line; a precharging circuit for precharging the array line and reference line at a preset precharging potential; at least one comparator having a first terminal connected to the array line, and a second terminal connected to the reference line; and an equalization circuit for equalizing the potentials of the array line and reference line in the precharging step. In addition, the reading circuit includes an equalization line distinct from the reference line; and controlled switches for connecting, in the precharging step, the equalization line to the array line and to the reference line, and for disconnecting the equalization line from the array line and from the reference line at the end of the precharging step.

Abstract: A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.

Abstract: A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.

Abstract: A method of arbitration among a plurality of n units which seek access to a resource is regulated according to grants identified by means of an arbitration method, which compares between one another the priorities, generating, for each pair of the units comprising in general a unit x and a unit y with respective priorities Px and Py, a selection signal at a high level if the result of the operation Px>=Py is true. The method generates, for the pairs of the units, respective cross-request signals and generates the grant for the ith unit as a logical product of all the cross-request signals req i x with x ranging from 1 to n, excluding the case of x=i.

Abstract: The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective word line switching between a first operating voltage, in turn switching at least between the supply voltage and a programming voltage higher than the supply voltage, and a second operating voltage, in turn switching at least between the ground voltage and an erase voltage lower than the ground voltage. Each biasing circuit includes a level translator circuit receiving at the input the row selection signal and supplying as output a control signal switching between the first and the second operating voltages and an output driver circuit receiving as input the control signal and supplying at the output the biasing signal.

Abstract: Dummy cell test circuit for measuring delay times in embedded, said embedded circuits being connected to access circuits equipped with input access pads and output access pads, between which is comprised an electrical main path, said test circuit comprising a test input pad and a test output pad, between which is comprised an electrical dummy test path. According to the present invention the test input pad correspond to the access input pad (IN1′ IN1″) of the embedded circuit (2).

Abstract: The present invention includes a linear regulator with a Darlington bipolar output stage. The linear regulator includes a starting circuit, an output stage, and a reference voltage generator connected to a control loop. The starting circuit has output terminals connected to current sources and an input terminal connected to an input reference terminal of the linear regulator via a transistor of the PNP-type. The output stage includes two Darlington-connected transistors. The reference voltage generator supplies a voltage value approximately equal to the chosen output voltage value of the linear regulator. The control loop is configured as a voltage follower, which receives a reference voltage value from the reference voltage generator.

Abstract: A flash EEPROM memory cell comprises source and drain regions defining a channel region therebetween, a floating gate and a control gate. The source and drain regions are first and second doped semiconductor regions of a first conductivity type formed in a first active area region of a semiconductor material layer of a second conductivity type; the control gate comprises a third doped semiconductor region of the first conductivity type formed in a second active area region of the semiconductor material layer; and the floating gate comprises a polysilicon strip insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region.

Abstract: An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.

Abstract: A current amplifier includes an input branch having a first input; an output branch coupled to said input branch; a bias branch suitable for biasing said input branch. The input branch comprises at least one switch commanded by a first bias voltage supplied by said bias branch so as to substantially block the current flowing in said input branch and consequently substantially block the current flowing in said output branch when the current applied to said first input is null.

Abstract: A drive circuit for controlled edge power elements is described. In one embodiment the drive circuit for controlled edge power elements comprises: a first integrating circuit having a first input suitable for receiving in input a first drive signal; an integrating capacitor coupled to said integrating circuit; a first power element driven by said first integrating circuit and suitable for driving a load, said load having a first terminal. The said first integrating circuit includes a first current amplifier and said integrating capacitor is coupled between said first input and a predetermined reference voltage.