Abstract: Testing a CMOS integrated circuit includes establishing a current threshold value, powering the integrated circuit in static and idle conditions, measuring the current absorbed by the integrated circuit and comparing this with the threshold value and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured is respectively lower or higher than the threshold value. To improve discrimination between non-faulty and faulty devices, the threshold value is obtained by forming two measurement transistors in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents.

Abstract: The invention relates to a process for manufacturing a light sensor device in a standard CMOS process, including, implanting active areas on a semiconductor substrate to obtain a first integrated region of a corresponding photosensor; and forming a stack of layers having different thickness and refractive index layers over the photosensor to provide interferential filters for the same photosensor. At least one of the above mentioned layers is formed by a transparent metallic oxide having a high refraction index and a corresponding high dielectric constant. In this manner, due to the transparency of the high refraction index material, the design of interferential resonators is rendered more flexible making possible the use of a stack of layers including more than one high refraction index layer.

Abstract: A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal.

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract: A method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate is presented. The method includes forming several regions projecting from the substrate surface and aligned to one another, and forming a fill layer in the gaps between the projecting regions. The fill layer is planarized to expose the regions, and a portion of the regions is removed to form holes at the locations of the regions. Next an insulating layer is formed in the holes. The insulating layer is selectively removed to form spacers along the edges of said holes and at least one conductive layer is deposited over the exposed surface. Later, a step of photolithograpy with a mask is performed and the conductive layer is etched to define lines and collimate them to the underlying regions.

Abstract: A DC-DC converter including a current error amplifier and a voltage error amplifier connected in parallel to control the charging phase of the battery, during which a charging current is supplied to the battery to bring the voltage of the battery gradually up to a full charge voltage; a charging interruption stage for interrupting the charging phase before the voltage of the battery has reached the full charge voltage; and an activation stage for activating the charging interruption stage when the full charge voltage is close to the supply potential at which the supply line of the current error amplifier is set.

Abstract: A method of manufacturing an SOI (silicon on insulator) wafer includes the step of selective anisotropic etching to form, in the substrate, trenches which extend to a predetermined depth from a major surface of the substrate and between which pillar portions of the substrate are defined. The method further includes the step of selective isotropic etching to enlarge the trenches, starting at a predetermined distance from the major surface, thus reducing the thicknesses of the pillar portions of the substrate between adjacent trenches. Also, the method includes the steps of selective oxidation to convert the pillar portions of reduced thickness of the substrate into silicon dioxide and to fill the trenches with silicon dioxide, starting substantially from the predetermined distance, and epitaxial growth of a silicon layer on the major surface of the substrate.

Abstract: A method for realizing alignment marks on a semiconductor device employs a thicker dielectric layer than in the prior art. The method is used during a manufacturing process including at least a Chemical Mechanical Polishing process step, and includes forming alignment marks on a portion of a semiconductor substrate; masking the marks portion during a further deposition step of a first conductive layer covered by a first dielectric layer; depositing a first conformal metal layer over the first dielectric layer and over the marks portion; depositing a second dielectric layer over the first metal layer; and performing a CMP process step to planarize the second dielectric layer; wherein the thickness of the first dielectric layer is high enough that the second dielectric layer covers the alignment marks portion under the level of the first dielectric top surface thereby preventing the CMP process step to planarize the marks portion.

Abstract: A memory counter circuit includes a plurality of mutually connected counter stages, an internal address bus interfaced with each one of the counter stages for sending an external address signal to each one of the counter stages, a circuit for loading the external address signal onto the internal address bus, and an enabling circuit for enabling a connection between the internal bus and each one of the counter stages. The enabling circuit may be driven by a true address latch enable signal. The memory counter circuit may further include a circuit for generating the true address latch enable signal starting from an external address latch signal and a fast address latch enable signal for driving the circuit for loading the external address signal onto the internal address bus. A signal generation circuit may also be included for generating clock signals for synchronizing each one of the counter stages. The synchronization signals are preferably not simultaneously active.

Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Abstract: A manufacturing process including: forming a first insulating region on top of an active area; forming a tunnel region at the side of the first insulating region; depositing and defining a semiconductor material layer using a floating gate mask to form a floating gate region. The floating gate mask has an opening with an internal delimiting side extending at a preset distant from a corresponding outer delimiting side of the mask, so that the floating gate region forms inner a hole, and the tunnel region is defined, as regards its length, by the floating gate ask alone. The hole is filled with a dielectric material layer. The surface of the floating gate region is planarized, and an insulating region of dielectric material is made. A control gate region and conductive regions in the active area are then formed.

Abstract: Method of fabrication of a no-field transistor with no extra process costs, providing for defining an active area for the transistor surrounded by a thick field oxide layer, insulatively placing a polysilicon gate electrode across the active area to define source/drain regions of the no-field transistor, providing an implant protection mask over a boundary between at least one of the source/drain regions and the field oxide layer, selectively implanting in said source/drain regions a relatively heavy dose of dopants to form relatively heavily doped source/drain regions and to simultaneously dope the polysilicon gate electrode, the polysilicon gate electrode formed with lateral wings extending towards the at least one source/drain region, and the implant protection mask extending over the lateral wings but not over the polysilicon gate.

Abstract: The invention relates to a Class AB operational amplifier providing both output gain enhancement and adaptative output bias. The operational amplifier includes first and second output terminals; a main differential stage having first and second differential inputs and a first differential output stage; a first adaptatively biased, boosted output stage coupling the first differential output stage to the output terminal. Each output stage includes a first NMOS output transistor having a control terminal, a first terminal coupled to the respective output terminal, and a second terminal, and includes a first output amplifier having a first input coupled to the second terminal of the first output transistor, a second input coupled to the first differential output stage to provide adaptative bias for the first boosted output stage, and an output coupled to the control terminal of the first output transistor.

Abstract: A switching voltage regulator includes a metal oxide semiconductor (MOS) power switch and driver circuit therefor. The MOS power switch may include a plurality of n power transistors each connected in parallel with one other. In particular, the first of the plurality of power transistors may have a larger size than the other power transistors. More specifically, the respective sizes of the individual power transistors may scale down from one to the next. In this way, an equivalent size of the power switch is greatly reduced with respect to prior art switches in that the first and largest transistor may be readily turned off. This may be carried out without substantially affecting the delivered current, which continues to be supplied by the remaining transistors. Further, a transconductance of the power switch may decrease as the power transistors are turned off in order from the first through the nth power transistors.

Abstract: A converter that is directly connectable to an AC power source (e.g., the mains) includes a rectifier stage for rectifying a network voltage, a power factor correction pre-regulating circuit supplied with the rectified network voltage for producing a DC voltage of a predetermined nominal value on an output node, and a DC-DC converter. The DC-DC converter may be supplied on an input node thereof with the DC voltage of the predetermined nominal value for producing a regulated DC voltage on an output node thereof. The DC-DC converter may use a clock whose frequency is selected between at least one low and one high value by a selection signal. Furthermore, the converter may also include a stand-by circuit for producing the selection signal based upon the current delivered to the load.

Abstract: A polymeric composition for making semiconductor device packaging includes at least one epoxy resin, at least one curing agent in an amount between 30 and 110 parts by weight per 100 parts by weight of the epoxy resin, at least one silica-based reinforcing filler in an amount between 300 and 2300 parts by weight per 100 parts of the epoxy resin, and at least one control agent for a rheology of the polymeric composition. The at least one control agent may be substantially free from polar groups and present in an amount between 0.1 and 50 parts by weight per 100 parts by weight of the epoxy resin. The invention also relates to a plastic packaging material for microelectronic applications which may be obtained from the above polymeric composition, and to a semiconductor electronic device including such packaging material.

Abstract: A frequency doubler circuit with a 50% duty cycle output includes a two-input XOR or XNOR logic gate having a first input coupled to a digital input signal having a first frequency, and a second input coupled to a replica of the input signal delayed by a quarter of the time period of the input signal. The frequency doubler circuit includes at least two capacitors in series, a constant current generator for charging the capacitors during one of the two half periods of the input signal, and first and second switches controlled in phase opposition by the input signal and by an inverted signal thereof for charging and discharging the capacitors during each period of the input signal. A voltage divider halves the voltage present on the capacitors so that a comparator senses the halved voltage on one of the two capacitors. The comparator provides an output signal to the second input of the logic gate.

Abstract: A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.

Abstract: A voltage converter circuit with a self-oscillating half-bridge configuration has a first and a second input terminal, and a first and a second output terminal, and including: a first power switch coupled between the first input terminal and the first output terminal, a second power switch coupled between the first output terminal and the second input terminal, a first voltage sensor having a first and a second sensing terminals coupled between the first input terminal and a control terminal of the first power switch, and a second voltage sensor having a first and a second sensing terminals coupled between the first output terminal and a control terminal of the second power switch. Each voltage sensor detects a voltage variation supplied on its respective first sensing terminal and generates on the respective second sensing terminal an activation potential for the respective power switch.

Abstract: A method of modifying the threshold voltages of a plurality of non-volatile memory cells, for example, flash EEPROM memory cells, after an erasure operation, is described. In order to perform the equalization quickly and to optimize the use of the voltage supplies for biasing the columns, the method provides for the following steps: connecting all of the column lines to a voltage supply, monitoring the supply voltage, and applying, to all of the row lines, a voltage variable from a predetermined minimum value to a predetermined maximum value, the rate of change being regulated to maintain the supply voltage of the column lines at a substantially constant, predetermined value. The same method can be used for reliable and quick programming of a memory of the flash EEPROM type, or of another type.